Patents Represented by Attorney, Agent or Law Firm Peter T. Rutkowski
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Patent number: 5025416Abstract: A magnetic memory element is fabricated from a thin magnetic film wherein the magnetic film is grown on a lattice-matched substrate and subsequently patterned to form a closure domain. The closure domain is comprised of a plurality of legs which are joined at domain walls. The individual legs are patterned in the thin magnetic film to lie parallel to an easy axis of the thin film crystal structure being used. Thus, each closure domain represents a magnetic memory element. Fringing fields about the memory elements are eliminated due to the closure domain design. An array of such closure domains can be grown on a substrate and can be packed to high densities up to the limits of current lithographic technology. Such thin film magnetic memory arrays are non-volatile and are compatible with existing RAMs.Type: GrantFiled: June 1, 1989Date of Patent: June 18, 1991Assignee: The United States of America as represented by the Secretary of the NavyInventor: Gary A. Prinz
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Patent number: 5013681Abstract: A process for fabricating thin film silicon wafers using a novel etch stop composed of a silicon-germanium alloy includes properly doping a prime silicon wafer for the desired application, growing a strained Si.sub.1-x Fe.sub.x alloy layer onto seed wafer to serve as an etch stop, growing a silicon layer on the strained alloy layer with a desired thickness to form the active device region, oxidizing the prime wafer and a test wafer, bonding the oxide surfaces of the test and prime wafers, machining the backside of the prime wafer and selectively etching the same to remove the silicon, removing the strained alloy layer by a non-selective etch, thereby leaving the device region silicon layer. In an alternate embodiment, the process includes implanting germanium, tin or lead ions to form the strained etch stop layer.Type: GrantFiled: September 29, 1989Date of Patent: May 7, 1991Assignee: The United States of America as represented by the Secretary of the NavyInventors: David J. Godbey, Harold L. Hughes, Francis J. Kub
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Patent number: 4979798Abstract: The acoustic pressure sensitivity of an optical fiber waveguide is maximized by surrounding it with an outer coating which is selected from a material having high Young's modulus and low bulk modulus.Type: GrantFiled: October 18, 1989Date of Patent: December 25, 1990Assignee: The United States of America as represented by the Secretary of the NavyInventors: Nicholas Lagakos, Joseph A. Bucaro
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Patent number: 4964946Abstract: A process for fabricating self-aligned field emitter arrays using a self-eling planarization technique, e.g. spin-on processes, is disclosed which includes the steps of depositing a dielectric layer on top of an array of field emitters, depositing a thin conducting film over the dielectric layer, and applying a planarization layer on the thin conducting film. Thereafter the structure is selectively etched until the underlying conducting layer is exposed in regions surrounding the field emitters, thereby defining the grid apertures. The conducting layer and dielectric layer are then selectively etched sequentially to a depth sufficient to expose a field emitter cathode tip at each field emitter site. This invention uses the concept of a self-leveling, planarizing material to define the grid apertures.Type: GrantFiled: February 2, 1990Date of Patent: October 23, 1990Assignee: The United States of America as represented by the Secretary of the NavyInventors: Henry F. Gray, George J. Campisi
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Patent number: 4937584Abstract: A method of nulling out interference sources in a large-aperture phased ay radar system is described. The system has apriori knowledge of the interference sources and depends upon access to the array element phase shifters for injection of phase only or phase and amplitude perturbations, of a mainbeam aperture distribution, into said array element phase shifters. The phase or phase and amplitude perturbations are derived from an aperture ripple modulation algorithm. The system does not require any auxiliary elements or correlators or beamformers.A method of nulling out interference sources in a monopulse large-aperture phased array radar system is also described wherein the phase only or phase and amplitude perturbations are injected into both the sum and difference beams.Type: GrantFiled: December 22, 1988Date of Patent: June 26, 1990Assignee: United States of America as represented by the Secretary of the NavyInventors: William F. Gabriel, Theodore C. Cheston
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Patent number: 4932783Abstract: An apparatus for minimizing polarization-induced signal fading in an interferometric fiber-optic sensor is disclosed. The apparatus includes an optical source for providing an input light beam, a polarization modulator for modulating the state of polarization of the input light beam into at least three states represented by mutually perpendicular polarization vectors on a Poincare Sphere. The apparatus further includes means for conveying the input light beam with the at least three mutually perpendicular modulated states of polarization to the fiber-optic sensor, the interferometric fiber-optic sensor being responsive to the input light beam with modulated polarization states for developing an interference pattern output, wherein the interference pattern output has at least three visibilities corresponding to the input states of polarization.Type: GrantFiled: July 21, 1989Date of Patent: June 12, 1990Assignee: United States of America as represented by the Secretary of the NavyInventors: Alan D. Kersey, Michael J. Marrone
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Patent number: 4924285Abstract: An integrated, planar, single-channel, photodetector-amplifier device is disclosed. The single-channel device includes a photodetector layer and an amplifier layer above the photodetector layer. The photodetector layer is low-doped to give a low dark current and is sufficiently thick to give a high quantum efficiency. The amplifier layer is of a smaller thickness and is a more highly doped material than the photodetector layer, to provide an amplifier having high gain. An insulating layer is included between the photodetector and amplifier layers for electrically isolating the photodetector and amplifier layers. The layers are fabricated on a substrate. Isolation regions are also included for electrically laterally isolating a photodetector, amplifier, and other circuit components comprising the single channel device from each other.Type: GrantFiled: October 25, 1988Date of Patent: May 8, 1990Assignee: The United States of America as represented by the Secretary of the NavyInventors: Gordon W. Anderson, John B. Boos, Harry B. Dietrich, David I. Ma, Ingham A. G. Mack, Nicolas A. Papanicolaou
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Patent number: 4914442Abstract: A method of preserving targets in the clear in an adaptive baseband MTI radar system with pulse compression is disclosed. The angle of the weighting signal is determined from the inverse tangent of the inphase and quadrature components of the weighting signal. This angle is then compared to a threshold angle in order to generate a modified weighting signal.Type: GrantFiled: January 30, 1989Date of Patent: April 3, 1990Assignee: The United States of America as represented by the Secretary of the NavyInventors: Frank F. Kretschmer, Jr., Bernard L. Lewis
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Patent number: 4888626Abstract: A self-aligned GaAs FET with an active channel which is unaffected by sure charge trapping/emission. The device comprises a channel of n-doped GaAs, a source and drain regions of n.sup.+ GaAs disposed at opposite ends of the channel, a semi-insulating GaAs layer disposed over the channel, with this GaAs layer having open first and second end surfaces disposed at an angle of greater than or equal to 45.degree. relative to the channel plane. A cavity is disposed in the GaAs layer exposing a portion of the channel, and a gate metallization is disposed over the GaAs layer and extending from the first end surface to the second end surface of the GaAs layer and directly contacting the exposed portion of the channel region in the cavity to form a Schottky barrier contact. This gate metallization is not disposed in contact with a significant portion of either of the first and second end surfaces.Type: GrantFiled: April 17, 1987Date of Patent: December 19, 1989Assignee: The United States of America as represented by the Secretary of the NavyInventor: John E. Davey
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Patent number: 4856095Abstract: A field-effect transistor performs four functions, namely signal demodulation, generation of a local oscillator signal, generation of harmonics of this local oscillator signal through frequency multiplication, and mixing of the demodulated signal with either the local oscillator signal or one of its harmonics to produce a signal at a lower intermediate frequency; the field-effect transistor being the key element in a demodulator-downconversion circuit.Type: GrantFiled: May 28, 1987Date of Patent: August 8, 1989Assignee: The United States of America as represented by the Secretary of the NavyInventor: Christen Rauscher
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Patent number: 4850098Abstract: A fiber optic sensor using the treated coil of optical fiber as a structural support system for the sensor, and a method for making such a sensor.Type: GrantFiled: April 15, 1988Date of Patent: July 25, 1989Assignee: The United States of America as represented by the Secretary of the NavyInventor: Aileen M. Yurek
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Patent number: 4803687Abstract: A carbon layer between a neon layer and a sodium layer serves as a thermal buffer therebetween to enable the neon layer to remain at a lower temperature and density to allow for the generation of coherent x-rays. A high powered laser heats the sodium layer which acts as a flashlamp for direct photon pumping of the neon layer. The neon layer, heated by a lower powered laser, then lases at about 58, 82, and/or 230 angstroms.Type: GrantFiled: November 7, 1985Date of Patent: February 7, 1989Assignee: The United States of America as represented by the Secretary of the NavyInventors: Frederick Cochran, Jack Davis, John Aprugese
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Patent number: H873Abstract: A method of making a Josephson Junction is disclosed which includes the steps of depositing a base electrode layer of a refractory superconducting material on a substrate, depositing a first passivation layer on the base electrode, depositing a barrier layer of refractory insulating semiconducting material on the passivation layer, depositing a second passivation layer on the barrier layer, and depositing a counter electrode on the second passivation layer. The layers are deposited at a substrate temperature of from about 50.degree. C. to about 700.degree. C. in an Ultra-High Vacuum sputtering system at a base pressure of less than or equal to 5.times.10.sup.-8 Torr. In the preferred embodiment a base electrode and counter electrode of NbN are separated by a barrier layer of hydrogenated silicon. When exposed to high post processing temperatures this structure maintains a chemically stable interface with the substrate.Type: GrantFiled: June 30, 1989Date of Patent: January 1, 1991Assignee: United States of AmericaInventors: Edward Cukauskas, William Carter