Abstract: A method for constructing a semiconductor-on-insulator is provided. A sacrificial layer (12) of a predetermined thickness is first formed on a semiconductor wafer (10) surface. The wafer (10) is then subjected to an ion implantation process to place the ions (16) at predetermined depths below the semiconductor wafer surface. During the implantation process, the sacrificial layer (12) is gradually sputtered away and thereby compensating the gradual outgrowth of the silicon surface due to the volume of the implanted ions (16). A post-implant anneal is performed to allow the ions (16) to react with the semiconductor to form a buried insulating layer (24).

Abstract: A test structure and a method of using it for measuring submicron linewidths. Diffraction gratings are made with lines having an unknown linewidth. The grating has a pitch comprises of multiple lines and multiple spaces. This permits a wider "effective pitch" resulting in an increased number of observable diffraction orders. Each order provides an intensity measurement, which can be substituted into a diffraction intensity equation in which intensity is a function of linewidth and other unknown variables. At least as many intensity measurements are obtained as are unknown variables so that a system of equations can be solved for the linewidth. In practice, if the grating lines are made in the same manner as other lines of a product, the width of the latter can be inferred.

Abstract: Voltage minimizer and maximizer circuits are provided for both single-ended and fully-differential analog input voltages. A single-ended analog voltage maximizer circuit includes a plurality of operational amplifiers (OP.sub.1, OP.sub.2 . . . OP.sub.N) wherein the number of operational amplifiers corresponds to the number of separate voltages (V.sub.1, V.sub.2 . . . V.sub.N) from which a maximum voltage is to be determined, each of the operational amplifiers receives a single-ended analog voltage at its non-inverting input, each output of the plurality of operational amplifiers is connected to a common output line where the maximum analog voltage output (V.sub.0) will be received, the common output line is also connected to the inverting input of each of the operational amplifiers. Each operational amplifier also has an operational amplifier circuit (FIGS.

Abstract: A memory device (10) having a precharge and timing control circuit (24) is configured so that a precharge state occurs at the end of memory cycles. A precharge signal remains active until a change of address is detected by an address transition detector (14). This address change causes a word line controller (86) to activate memory word lines (20), a precharge controller (82) to deactivate the precharge signal, and a sense amp latch controller (88) to enable sense amplifiers within a write and sense amplifier control circuit (38). After a sufficient amount of time has transpired for either a write operation to occur or for valid data to be detected in the sensing amplifiers, the word line controller (86) deactivates the word lines (20), the sense amp latch controller (88) latches the sense amplifiers, and the precharge controller (82) activates the precharge signal.

Abstract: A source and method for generating high density plasma with inductive radio-frequency power coupling is provided in which coil antenna sections (34) within a plasma source (12) are used to generate a high-density uniform plasma. This plasma is then guided into transferred in a transfer chamber (14) and then to a processing chamber (16). Within the processing chamber (16), the plasma reacts with a semiconductor wafer (18) or another workpiece for plasma-enhanced deposition or etch processing.

Abstract: An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.

Abstract: An unerasable memory cell (10) is formed in the face of a layer (22) of semiconductor of a first conductivity type and includes an erasable read-only memory cell (12) having a first source/drain region (16) and a second source/drain region (18) of a second conductivity type opposite the first conductivity type. First source/drain region (16) is spaced from second source/drain region (18) by a channel area (24). A floating gate conductor (20) is disposed insulatively adjacent channel area (24) and a control gate conductor (22) disposed insulatively adjacent floating gate conductor (20). A heavily doped moat (32) of the second conductivity type laterally surrounds memory cell (12). A load device (14/66) couples moat (32) with first source/drain region (16) of a memory cell (12).

Abstract: This is a method of testing (burn-in and/or stress test) any portion, preferably all, of a plurality of memory cells and the pass gates of transistors (i.e. item 38 of FIG. 2) connecting the memory cells (i.e. item 40 of FIG. 2) to datalines (i.e. item 26) of a memory device. The method is comprised of: accessing every memory cell of the portion of the plurality of memory cells; supplying, preferably by a source external to or internal to the memory device, a positive voltage, preferably greater than that used during normal usage, to a first electrode (i.e. item 46 of FIG. 2) of every accessed memory cell concurrently with supplying, preferably by a source either external to or internal to the memory device, a lower voltage, preferably around zero volts, to the other electrode (i.e. item 44 of FIG.

Abstract: A semiconductor device is formed without using a leadframe. A semiconductor device is formed in one area of a semiconductor chip and a second area includes conductors to which lead wires are bonded. The lead wires are used for mounting the semiconductor device.

Abstract: An electron beam imaging system (10) includes a photoemitter plate (12). An optical image beam (15) is directed through a pattern mask (18), which is imaged onto the photoemitter (12). The photoemitter (12) emits electrons from those unmasked regions illuminated by the optical image beam, emitting an extended-source electron beam that carries the mask image. The extended-source electron beam is focused (34) onto a device under fabrication (40), providing a single-stage electron lithographic patterning function. The optical source (16) is chosen so that optical image beam energy is nearly identical to the work function for the photoemissive coating (14) of the photoemitter (12). As a result, the photoemitter (12) emits electrons with substantially zero kinetic energy, allowing the emitted electrons to be accelerated through the electron beam focusing elements (34) with very nearly identical electron velocities, thereby minimizing chromatic aberrations.

Abstract: An address match scheme is disclosed which allows the alternate selection of fuses blown based on either logic ones or logic zeros in an address.

Abstract: An improved memory cell (118) is provided which may be incorporated into an array (202) of memory cells. Array (202) includes a first gate conductor region (224) and a second gate conductor region (238), wherein the first and second gate conductor regions are orthogonal to one another. Each one-half of the cell may include two series transistors connected to a cross-coupled trench transistor. Cross-coupling of the trench transistors is effected through the use of parallel local interconnect regions (256) and (258).

Abstract: A transistor (10) having a gate region formed with a thin oxide layer (28) over the gate (24). The gate (24) has a polysilicon spacer (34) formed adjacent to the gate (24) for increasing the resistance to channel hot-electron-induced degradation.

Abstract: A non-volatile memory cell includes heavily doped source 12 and drain 14 regions separated by a channel region 16. The source 12 and drain 14 are isolated from floating gate 18 and control gate 22 by thick oxide 36. A floating gate 18 is formed over and insulated from a portion of said channel region 16 adjacent to the source 12 and a control gate 22 is formed over and insulated from the floating gate 18 and the remaining portion of the channel region 16. The cell is programmed by applying a nearly reference voltage V.sub.s to the source region 12 and applying a drain voltage V.sub.D to the drain region 14. A gate voltage V.sub.G is applied to the control gate 22 such that an inversion region 15 is formed in the remaining portion of said channel region 16 such that the floating gate 18 is charged up by hot electron injection on the side away from the source junction. The source junction is self aligned to floating gate and is graded for efficient erase. Other key features and methods are also disclosed.

Abstract: Trace amounts of oxygen are removed from a plasma reactor by heating a filament during the times the reactor is not processing to cause the filament to react with the oxygen in the reactor, and forms an oxide of the filament material and the oxygen.

Abstract: An interferonmetric temperature measurement system is described for determining the temperature of a sample. The system comprises three detectors for measuring various intensities of a beam of electromagnetic radiation reflected off the sample and circuitry for determining the temperature from the intensities. The detectors measure the intensity of the beam and two orthogonally polarized components of the beam.

Abstract: The invention is an improved layout for integrated circuits employing local interconnect pads, particularly six-transistor SRAM circuits, comprising a local interconnect pad which electrically bridges two segments of a conducting line and an active device, and a method for employing the layout.

Abstract: A memory cell comprises a semiconductor pillar comprising an inversion layer formed on a side wall of the pillar. A conductive capacitor of the memory cell comprises a first electrode formed by the inversion layer. A transistor of the memory cell is formed in the pillar and comprises a first source/drain region, a gate, and a second source/drain region comprising the inversion layer. The gate is coupled to a control line partially overlying a top end of the pillar.

Abstract: A gyroklystron device includes an electron beam source, a plurality of bunching cavities and an output cavity. A first bunching cavity has an input coupling aperture for receiving an rf signal from an rf signal injecting source. Each of the bunching cavities has a first pair of substantially uniform-angle slots of a preselected angle, which are diametrically opposed, and extend axially, parallel to the direction of the electron beam and extend into drift regions on both sides of the cavities. The first pair of slots control the Q of a desired mode and higher order modes. A second and third pair of slots are diametrically opposed and extend axially, parallel to the direction of the first pair of slots, but are rotated 90 degrees circumferentially from the first pair of slots. These slots control the axial profile of any mode that leaks out beyond the desired mode and control the length of field interaction with the electron beam.

Abstract: A surface floating buoy has an antenna attached to a linkage system which pivots about the floating buoy. The linkage system is attached to a counterweight such that the antenna is maintained at a desired vertical position with respect to the surface of a body of water by pantographic action. The floating buoy contains a hollow cavity of sufficient size to hold the linkage system antenna and counterweight prior to deployment in a body of water. Upon deployment in the water, gravitational forces on the counterweight and linkage system cause the system to be deployed. The invention may also include a servo feedback system for more accurately positioning the antenna at its desired position.