Abstract: An asynchronous transmission mode (ATM) memory array capable of storing one ATM packet of data is an n x m array of memory locations, each memory location capable of storing one bit. The array has n columns, where n is the number of bits in an ATM cell of data, and m rows, where m is the number of cells in an ATM packet. The memory array has a plurality of input lines, one for each of said n columns, which together receive n bits simultaneously. It also has n ground lines, one for each of said n columns in said array, each ground line connected to one memory location in each of said n columns in its row; such that each ground line carries the current of only one bit, thereby reducing the noise transients.
Abstract: The present method is a decoding scheme for suppressing excessive amount of zeroes transmitted via a T1 line facility. Clear channel transmission capability is provided by this scheme for 32 kb/s or 64 kb/s transmission channels. This scheme provides the proper zero bit suppression for alternating mark inversion signaling (AMI). A proper AMI signal contains no more then 15 consecutive zero bit positions. In addition to meeting the AMI signaling standards, this scheme does not induce any violations of VMR (violation monitor and removal) equipment. Thus, this scheme is transparent to existing line equipment and error monitoring equipment. This scheme provides both a necessary and sufficient method for achieving the AMI signaling requirements during clear channel signaling.
September 2, 1986
Date of Patent:
May 24, 1988
GTE Communication Systems Corporation
Ernest E. Blondeau, Jr., Stephen J. Czarnecki
Abstract: A circuit divides pulse code modulation (PCM) samples in D2 format. An exponent subtractor provides the difference of the exponents of the two numbers. A mantissa multiplier circuit determines the quotient by multiplying the mantissa of the PCM sample by an inverted divider. A sign generator provides a sign value for the resultant quotient of the two numbers. A normalizer circuit ensures that the quotient mantissa has a predetermined range of values.
Abstract: An address generator which provides addresses for machine storage and software retrieval of computer status information. A counter is used to generate address signals in a descending order until it is disabled by a computer during alarm conditions. Under such conditions the counter provides a bias address for referencing the most recent status word. A gating circuit gates computer generated address signals to an adder circuit during the alarm conditions. The adder circuit adds the computer generated address signals to the counter generated bias signal to provide address signals which reference physical storage locations in a memory.
December 31, 1984
Date of Patent:
April 26, 1988
GTE Communication Systems Corporation
Robert J. Abrant, Michael D. Martys, George K. Tarleton
Abstract: A Current Reference for providing a feedback signal to a current driver in a current-series, feedback-controlled current source circuit that includes at least one, but more likely more than one, controlled current source. The Current Reference comprises a current mirror having an input transistor coupled to an output transistor in a current mirror configuration. The input transistor of the current mirror is driven by a constant current source, Icc, so that the current mirror output transistor causes a current substantially equal to Icc to flow out of a summing node. A sensing transistor is coupled to a controlled current source for providing a current into the summing node that is representative of the current delivered by the controlled current source. As a result, the current flowing away from the summing node and into a phase inverter is representative of the difference between the delivered current and Icc.
Abstract: An integrated circuit includes an interface circuit for coupling with a relative high-level VOICE circuit and a relatively low-level DIALER circuit to a subscriber line. A first shunt transistor is coupled across the telephone line and has its collector current forced by a current sink driven from the VOICE circuit. A second shunt transistor is coupled in a current mirror configuration to the first shunt transistor and supplies current to the DIALER circuitry. The interface circuit includes a saturation prevention circuit coupled to the current sink and to the second shunt transistor for sensing a tendency of the second shunt transistor toward saturation and for increasing the collector current load on that transistor in response. The saturation prevention circuit includes a voltage offset element and a sensing transistor arranged to form a loop with the collector-to-base junction of the second shunt transistor.
Abstract: A circuit multiplies pulse code modulation (PCM) samples in D2 format. An exponent adder provides the sum of the exponents of the two numbers. A mantissa multiplier circuit determines the product of the two mantissas and a sign generator provides a sign value for the resultant product of the two numbers. A normalizer circuit ensures that the product mantissa has a predetermined range of values.
Abstract: A circuit multiplies or divides pulse code modulation (PCM) samples in D2 format. An exponent adder/subtractor provides the sum/difference of the exponents of the two numbers. A mantissa multiplier/divider circuit determines the product/quotient of the two mantissas and a sign generator provides a sign value for the resultant product/quotient of the two numbers. A normalizer circuit ensures that the product/quotient mantissa has a predetermined range of values.
Abstract: This invention is a device which permits the percentage of real time consumed by software tasks of a telecommunications switching system or other process controller to be measured and displayed on a percentage meter. The relative percentages of different real time tasks are displayed by the relative intensities of particular lamps mounted on a control panel. The real time usage of non-standard, user defined, software tasks may be selected for display on the meter.
Abstract: An apparatus for enabling the performance loop resistance and DC balance checks on a subscriber line includes relay contacts coupled across the line terminals. The apparatus includes circuitry for detecting the application of an activating signal to the line and for optically coupling a resulting trigger signal to a pair of monostable timers. The timer output pulses are arranged so that the relay is energized subsequent to the removal of the activating signal and remains energized during an interval established by the relative durations of the timer output pulses.
Abstract: A remote isolation apparatus includes double-position switch for selectively coupling or isolating a telephone company central office and a multi-wire subscriber line. The switch operates according to a remotely originated activating signal so that, until the switch is operated, the central office is connected to the subscriber line through normally closed contacts. When the switch is operated, the central office TIP and RING leads are coupled to a reference terminal, and the central office is isolated from the subscriber line.The apparatus includes circuitry for detecting the application of an activating signal to the line and for optically coupling a resulting trigger signal to a pair of monostable timers. The timer output pulses are arranged so that the relay is energized subsequent to the removal of the activating signal and remains energized during an interval established by the relative durations of the timer output pulses.
Abstract: An interface circuit for transmitting data messages between a CENTREX equipped central office exchange and a remotely located attendant console. The interface circuit includes control and sense decoding circuitry arranged to output control signals to the interface circuit and transfer control signals and data messages to the CENTREX. Sequential memory connected to the control and sense decoding circuitry receives and stores from the CENTREX data messages responsive to an enabling signal from the CENTREX. The control and sense decoding circuitry signals a controller connected to the sequential memory that data messages have been loaded in the sequential memory. The controller then transfers the data messages out of the sequential memory and processes the received data messages, storing the data messages in a temporary memory. The controller transfers the data messages from the temporary memory to sending circuitry which transmits the data messages to the attendant console.
Abstract: This invention discloses a circuit for examining the value transmitted via a digital bus. A determination is made as to whether the value matches a predefined programmable value. An output indication is given for a match. In addition, this circuit may examine the transmitted value to determine whether it is within the bounds of a predefined range of values. This circuit utilizes a minimum of space and hardware components, due to its fabrication using RAM devices and a program logic array.
Abstract: Under normal operating conditions in an on-linne active/off-line standby duplicated processor system, only the on-line active processor is permitted access to the system's bus structure. The off-line standby processor is disconnected from the system buses. A technique is shown that allows the off-line standby processor diagnostic access to the system peripherals via the bus structure. The standby processor may then perform diagnostic testing to determine its communication ability with the system's peripheral devices. The diagnostic testing is done rapidly to avoid any loss of processor throughput. This technique also assures that the diagnostic testing will not cause faults or after the system configuration during this testing. As a result, when the off-line processor is put into active service, this transition will be made smoothly since this processor's operation has been previously verified.
Abstract: A control circuit for effecting the transfer of data messages between an interface circuit and a CENTREX equipped central office exchange. The central office exchange includes a peripheral processor and the interface circuit includes an input and an output sequential memory for receiving and sending respectively, data messages to the peripheral processor. An input control circuit includes a first gating means having inputs connected to the peripheral processor and which produces an output signal responsive to the simultaneous application of a first and a second control signal. First bistable memory means receives the gating means output signal and further includes a clock input connected to a write select signal from the peripheral processor. Responsive to the write select signal, the gating means output signal is stored in the first bistable memory means. Second bistable memory means connected to the first bistable memory means output includes a clock input connected to a source of clocking signals.
Abstract: An improved loop current supply circuit including a first amplifier connected to a source of bias voltage. The first amplifier is further connected to a subscriber loop circuit through the tip and ring conductors. The first amplifier receives the bias voltage and supplies loop current to the loop circuit. A second amplifier connected to the tip and ring conductors outputs a voltage representative of the amount of current in the subscriber loop. When the output voltage of the second amplifier becomes greater than the bias voltage, a loop voltage network connected to the second amplifier and to the bias voltage source shunts the bias voltage from the first amplifier, decreasing the current in the loop circuit.
Abstract: An improved AC impedance matching arrangement including a first amplifier connected to a subscriber loop through the tip and ring conductors of a subscriber line circuit. The first amplifier is arranged to supply loop current to the subscriber loop through first and second resistors. Each resistor having a set DC value. A second amplifier connected to the tip and ring conductors is arranged to develop and output a signal responsive to AC signals applied to the tip and ring conductors from the subscriber loop. A feedback circuit connected to the second amplifier is arranged to receive the second amplifier output signal and develop and output to the first amplifier an impedance matching signal. The impedance matching signal raises the impedance seen by the tip and ring conductors above the set DC value of the first and second resistors.
Abstract: An arrangement for connecting an array of individual electronic elements into a readily expandable matrix. The arrangement comprises a plurality of matrix slices with each slice including a set number of electronic elements as well as a row and a column buffer. The electronic elements of each matrix slice are diagonally connected to the elements of the adjacent matrix slice.
April 27, 1984
Date of Patent:
June 30, 1987
GTE Communication Systems Corporation
Christopher M. Burlingame, Thomas J. Perry
Abstract: This invention is a device which permits the percentage of real time consumed by software tasks of a telecommunications switching system or other process controller to be measured and displayed on a percentage meter. The relative percentages of different real time tasks are displayed by the relative intensities of particular lamps mounted on a control panel of a meter. Non-standard, user defined, software tasks may be selected for display on the meter. Software tasks which over-shoot a predetermined amount of time provide an indication of this by lighting one of a number of different lamps. Each of these lamps measures a predetermined amount of over-shoot time.
Abstract: This circuit provides for synchronizing duplex copies of processor controllers. Either controller may be active in the simplex mode. That is, one controller is actively operating and controlling processors, while the other controller is in a standby mode. In this situation, the synchronization circuit synchronize its clock to itself. When a previously standby controller is made active, the control inputs of the standby controller are manipulated such that, the clock of the standby controller is synchronized to the already active a controller's clock. Once synchronism is achieved, the controllers are said to be operating in a synchronized duplex mode. The synchronization circuit of each controller then continuously checks to insure that the two controller copies are operating synchronously. If a non-synchronous condition is encountered by one of the synchronization circuits, the circuit that detected the lack of synchronization is repeatedly forced to a particular memory location.