Abstract: The present invention is an approach for verifying the operation of read only memory digital pads associated with the switching network digital switching system. Any failures are detected and an indication is transmitted for fault detection and recovery.

Abstract: A transmit data formatter is provided for assembling a plurality of 8-bit data bytes into a data message containing a plurality of message bytes. The transmit data formatter includes a receive buffer which receives a data byte from a peripheral processor. A parallel to serial converter receives the data byte from the receive buffer and outputs the data byte serially. A serial to parallel converter receives the serial data byte and assembles the data byte into a partial message byte when seven data bits have been received. A horizontal parity generator connected to the parallel to serial converter develops a horizontal parity bit which is appended to the seven data bits forming a message byte.

Abstract: A receive data reformatter for a telecommunications switching system is shown for disassembling a data message to a plurality of 8-bit data bytes. The receive data reformatter is comprised of a parallel to serial converter which receives the data message one byte at a time which it subsequently outputs serially. A horizontal parity check circuit receives the serial data and is arranged to output an error signal when an error in parity is detected. A serial to parallel converter, connected to the serial output of the parallel to serial converter, receives the serial data and assembles the serial data into parallel form. A write buffer connected to the serial to parallel converter receives the assembled parallel data when eight data bits have been accumulated in the serial to parallel converter. The thus formed data byte is output to a peripheral processor of the telecommunications switching system.

Abstract: This invention is a circuit for detecting a framing pattern consisting of a pseudo random shift register sequence. This circuit utilizes an extremely long framing pattern without either a large amount of memory or the need to receive a large number of bits in order to recognize the framing pattern. The use of lengthy framing patterns minimizes the chance of false framing caused by patterns in bit positions other than the framing bit position. In addition, the incoming data stream may be connected directly to the shift register mechanism.

Abstract: An information panel assembly comprised of liquid crystal display devices, positioned on a mounting member and sandwiched between a cover member and a circuit member. Elastomeric connectors connect the liquid crystal display devices to drive circuitry on the circuit member. The cover member includes rear projecting members which are accepted by apertures on the circuit member and are disposed to engage threaded fasteners, locking the assembly together. A switch member including a matrix of membrane switches is mounted over the cover member connecting each switch to the circuit member thereby, selectively controlling the information displayed.

Abstract: A circuit terminating clip for mechanically retaining and electrically connecting a planer substrate such as a thick/thin film circuit to a printed wiring card. The terminating clip is characterized by a terminating body having planer sidewalls defining a hollow interconnecting post receiving area therebetween. A substrate spring member extends from a bottom edge of a front wall of the terminating body arranged to accept the edge of the substrate, connecting the substrate to the terminating body. A terminating pad member extending from the top edge of the front wall of the terminating body is soldered to the substrate retaining the terminating body to the substrate. Post spring members extending inwardly into the post receiving area engage an interconnection post which extends from the printed wiring card thereby retaining the terminating body to the printed wiring card.

Abstract: The present invention provides for synchronizing signals transmitted to two duplex copies of hardware from a common source. Signals sent from the source to the duplex copies of hardware may arrive asynchronously at the two copies and require synchronization. In addition, the duplex hardware may be validly operated in the simplex mode of operation, which requires no synchronization of the two hardware copies.

Abstract: A circuit interconnection device for mechanically retaining and electrically connecting a planer substrate such as a thick/thin film circuit to a printed wiring card. The circuit interconnection device is characterized by a generally rectangular device body having planer sidewalls defining a hollow interconnection post receiving area therebetween. A pair of ears extend from a bottom edge of a front wall arranged to have an edge of the substrate rest thereon. A pair of substrate spring members extend outward from a top edge of the front wall to engage the substrate retaining and connecting the substrate to the terminating body. A rear wall includes a pair of post spring members extending inwardly into the post receiving area engaging an interconnection post extending from the printed wiring card thereby retaining and connecting the terminating body to the printed wiring card.

Abstract: In a PCM telecommunications switching system, an arrangement for deriving a clock signal from incoming PCM data of a digital span is shown. This derived clock signal is synchronized and continuously locked to the incoming PCM data of the digital span. The present digital phase locking arrangement cyclically adjusts the derive clock signal so that on the average synchronism is maintained.

Abstract: An arrangement for interfacing the originating time stage (OTS) and terminating time stage (TTS) of a time and control unit (TCU) to the space stage of T-S-T digital switching system. The space stage includes an intra-path through the space stage as well as an interpath. The interface transmits PCM samples simultaneously from the OTS to both the intra and interpaths of the space stage. PCM samples from the space stage are received by an intra buffer and an inter buffer from the intra path and inter path respectively. A TCU control memory gates and connects either the intra buffer or inter buffer to the TTS.

Abstract: This circuit provides for synchronizing the internal clocks of at least two central processing unit process controllers. In order to synchronize the internal clocks of these central processing units (CPUs), the CPUs periodically execute a predetermined set of operating instructions which cause their internal clocks to coincide. This synchronization function is dynamic in that it is continually performed in an on-line fashion while the processors are performing their telecommunication process control function.

Abstract: An address sequencer and memory arrangement is shown for transferring data in the form of message bytes to and from a plurality of digital data links. The address sequencer and memory arrangement includes a memory circuit having a plurality of memory location areas associated with each of the plurality of digital data links. A counter circuit connected to the memory circuit is loaded with a preset count by a link processor complex. The counter increments and outputs to the memory circuit addresses which sequentially access each of the memory location areas, transferring each message byte to a data link output buffer for transmission over a respective one of the plurality of digital data links. Alternatively, the counter addresses sequentially each memory location area transferring a message byte to each memory location area from each of the plurality of digital data links via a data link input buffer.

Abstract: The present invention is an interconnection of a loop analysis test system (LATS) to a digital switching system. This arrangement includes the utilization of existing network units to establish a path connection from the computer of a LATS system to a measuring unit of the LATS system. This path through the digital switching system provides for the appropriate signaling requirements in order to simulate a telephone call to the digital switching system for connection to a subscriber. Another path is provided to connect the measuring unit to the subscriber line to be tested via a special access network. In addition, this arrangement includes a data base in the CPU switching system to provide for determining whether the connection of this path through the switching system is for a test access or for normal calling functions. The data base also records the interconnection of equipment such that the proper subscriber's line may be accessed when called by the LATS system.

Abstract: The present invention is an interconnection of a loop analysis test system (LATS) to a digital switching system. This arrangement includes the utilization of existing network units to establish a path connection from the computer of a LATS system to a measuring unit of the LATS system. This path through the digital switching system provides for the appropriate signaling requirements in order to simulate a telephone call to the digital switching system for connection to a subscriber. In addition, this arrangement includes a data base in the CPU switching system to provide for determining whether the connection of this path through the switching system is for a test access or for normal calling functions. The data base also records the interconnection of equipment such that the proper subscriber's line may be accessed when called by the LATS system.

Abstract: A cross-copy arrangement is shown for synchronizing parity clock signals in a duplex digital system. Each copy of the duplex system generates a local timing signal and a remote timing signal. The remote signal of each copy is crossed over and logically combined with the local timing signal generating a parity clock signal.

Abstract: An improved screen printing apparatus for printing conductive, resistive and insulative films to the surfaces of ceramic or glass substrates. The screen printing apparatus is characterized by a carriage having a substrate to be printed resting thereon and a frame member extending about the periphery of the carriage. A mesh screen having an emulsion layer is affixed to the screen and suspended over the substrate. The improvement comprising a pair of force absorbing members attached to the carriage in a space relationship to and on opposite sides of the substrate. A pair of rolling means are attached to opposite sides of a squeegee holder with each rolling means in registration with a respective force absorbing surface. A squeegee extends from a bottom surface of the squeegee holder intermediate the rolling means. As the squeegee holder is drawn across the screen each rolling means travels along a respective force absorbing member.

Abstract: In a telecommunications switching system, a thick film digital span conversion circuit is connected between a digital span and a switching network of the switching system. The circuit converts data, which is encoded for digital span use, to TTL logic coding for use by the switching network. The telecommunications switching system provides for duplicated data transmission through the switching network. Duplicated conversion circuits are employed in an active/standby configuration under CPU control. On-line replacement of a fault conversion circuit may be performed without a switching service interruption.

Abstract: Circuitry for validating the integrity of PCM data transmitted through a digital switching network is shown. The space stage of the switching system requires that appropriate data validity be maintained throughout. A parity scheme is employed to fulfill this requirement. For detection of invalid parity, an alarm notification is sent to the central processing unit (CPU) of the switching system. The CPU may then interrogate the space switching circuitry to determine the particular location of the parity failure. In addition, the circuitry provides for a testing feature, such that, the operation of the parity checking circuits may be validated.