Abstract: The electric device (1, 100) has a body (2, 102) having a resistor (7, 107) comprising a phase change material being changeable between a first phase and a second phase. The resistor (7, 107) has a first electrical resistance when the phase change material is in the first phase and a second electrical resistance, different from the first electrical resistance, when the phase change material is in the second phase. The body (2, 102) further has a heating element (6, 106) being able to conduct a current for enabling a transition from the first phase to the second phase. The heating element (6, 106) is arranged in parallel with the resistor (7, 107).

Abstract: A membrane (20) has a membrane axis (5) and a middle area (50), a central cup-shaped depression (52) being provided around said membrane axis (5), which depression (52) preferably has a connecting channel (53), wherein the middle area (50) comprises groups of stiffening grooves (54, 55, 56, 57) which extend parallel to radial directions and of which a first group of long stiffening grooves (54, 55, 56) extends up to the depression (52), said connecting channel (53) issuing into two of the long stiffening grooves (55, 56), thus interconnecting these two long stiffening grooves (55, 56).

Abstract: A testing approach involves selective application of clock signals to target circuitry. In an example embodiment (300), a target circuit (332) having logic circuitry that processes data in response to an operational clock signal (308) having at least one clock period, is analyzed for delay faults. Test signals are applied to the logic circuitry while the logic circuitry is clocked with a high-speed test clock (309) having several clock-state transitions that occur during at least one clock period of the operational clock (308). An output from the logic circuitry is analyzed for its state (e.g., as affected by delay in the circuitry). Delay faults are detected as a difference in state of the output of the logic circuitry. With this approach, circuits are tested using conventional testers (340) that operate at normal (e.g., slow) speeds while selectively clocking selected portions of the circuit at higher speeds for detecting speed-related faults therein.

Abstract: A technique includes forming a first well in a substrate and forming a second well in the substrate. The first well is electrically isolated from the second well. The technique includes forming an element in the second well to limit current between the first well and the substrate.

Abstract: All pointer-based accesses require first that the value contained in a pointer register to be read and then that value be used as an address to the appropriate region in random access memory (RAM). As implemented today, this requires two memory read access cycles, each of which takes at least one clock cycle and therefore this implementation does not allow single cycle operation. In accordance with an embodiment of the invention, when an access is performed to pointer memory to read the contents of a pointer, it is the shadow memory that is actually read and that returns the pointer value. Since the shadow memory is made up of pointer registers, a read access involves multiplexing out of appropriate data for the pointer address from these pointer registers to form a target pointer address.

Abstract: An increasing number of phases in multiphase converters causes an increase in requirements with respect to the control IC. According to the present invention, instead of deriving a new PWM signal for every single phase of the DC-DC converter, the single phases are clustered into groups (22, 24, 26). Within each group, the converters are operated on the basis of one PWM signal (PW M1, PW M2 . . . PW MN). Advantageously, this may allow to reduce the requirements with respect to the control IC and thus may allow the application of cheaper and smaller control ICs.

Abstract: The invention relates to a ferroelectric device (10) with a body (11) comprising a substrate (1) and a ferroelectric layer (2) provided with a connection conductor (3) on a side facing away from the substrate (1), which ferroelectric layer contains an oxygen-free ferroelectric material (2) and is used to form an active electrical element (4), in particular a memory element (4). Such a device forms an attractive non-volatile memory device. In accordance with the invention, a conductive layer (5) is present between the substrate (1) and the ferroelectric layer (2), which conductive layer forms a further connection conductor (5) of the ferroelectric layer (2), and the active electrical element (4) is obtained as a result of the fact that the ferroelectric layer (2) forms a Schottky junction with at least one of the connection conductors (3, 5).

Abstract: The semiconductor device has a security coating with embedded magnetic particles and magnetoresistive sensors. This renders possible a measurement of the impedance of security elements defined by magnetoresistive sensors and security coating. If initial values of the impedance are stored, actual values can be compared therewith to see if the device has not been electrically probed or modified. Such a comparison can be used to check the authenticity of the device.

Abstract: To provide a circuit arrangement for controlling a sensor by means of a power supply source which is connected to input terminals of the sensor, and an evaluation circuit which is connected to output terminals of the sensor, by means of which the current consumption of a sensor in the standby state can be reduced in a simple manner, the power supply source (14) is switchable between at least two current levels in dependence upon an output signal level (S) of the sensor (12).

Abstract: A memory accelerator module buffers program instructions and/or data for high speed access using a deterministic access protocol. The program memory is logically partitioned into ‘stripes’, or ‘cyclically sequential’ partitions, and the memory accelerator module includes a latch that is associated with each partition. When a particular partition is accessed, it is loaded into its corresponding latch, and the instructions in the next sequential partition are automatically pre-fetched into their corresponding latch. In this manner, the performance of a sequential-access process will have a known response, because the pre-fetched instructions from the next partition will be in the latch when the program sequences to these instructions. Previously accessed blocks remain in their corresponding latches until the pre-fetch process ‘cycles around’ and overwrites the contents of each sequentially-accessed latch.

Abstract: The present invention provides an array (20) of magnetoresistive memory elements (10) provided with at least one data retention indicator device (50). The at least one data retention indicator device (50) comprises a first magnetic element (51) and a second magnetic element (52) each having a pre-set magnetisation direction, the pre-set magnetisation direction of the first and second magnetic elements (51, 52) being different from each other. The first and second magnetic elements (51, 52) are suitable for aligning their magnetisation direction with magnetic field lines of an externally applied magnetic field exceeding a detection threshold value. According to the present invention, a parameter of the at least one data retention indicator device (50) is chosen so as to set the detection threshold value of the externally applied magnetic field to be detected.

Abstract: An amplifier bias circuit connectable to an amplifier device, comprising a first sensor device for sensing a first amplifier characteristic and for providing at a first sensor output a bias signal related to the first amplifier characteristic. The circuit further comprises a second sensor device for sensing a second amplifier characteristic and for providing at a second sensor output a bias signal related to the second amplifier characteristic. The first sensor output and second sensor output are each connected to an amplifier connect connectable to a bias input of said amplifier device.

Abstract: A voltage regulator configured to receive a supply voltage from a voltage supply and provide a regulated voltage to digital circuitry is provided. The voltage regulator comprises first circuitry configured to inhibit high frequency energy generated by the digital circuitry from transmitting into the voltage supply, second circuitry configured to inhibit low frequency energy generated by the digital circuitry from transmitting into the voltage supply, and third circuitry configured to maintain the regulated voltage at a substantially constant value in response to a current drawn by the digital circuitry.

Abstract: A VLIW processor comprising a plurality of functional units (1, 3, 5, 7), a distributed register file (9, 11, 13, 15) accessible by the functional units (1, 3, 5, 7), a partially connected communication network (17) for coupling the functional units (1, 3, 5, 7) and selected parts of the distributed register file (9, 11, 13, 15), characterized in that the VLIW processor further comprises a communication device (29) for coupling the functional units (1, 3, 5, 7) and the distributed register file (9, 11, 13, 15).

Abstract: An circuit arrangement and method for reducing the number of processing loops needed to generate an error correction parameter used in the Montgomery method. An initial input to a processing loop is set to a value equal to the modulus, left shifted one register position. Values of the working register are shifted multiple positions during a single loop iteration, and a shifted result is subtracted and compared to zero to determine subsequent contents of the working register.

Abstract: In an electroacoustic transducer (1), an annular shaped magnet system (14) is provided, enclosing an inner space (22), in which inner space (22) an integrated circuit (31) is accommodated, with the aid of which integrated circuit (31) an electrical signal to be sent to a moving coil (29) of transducer (1) can be amplified.

Abstract: A cross coupled folding circuit comprises a reference voltage circuit to supply m reference voltages, an amplifier circuit to provide control signals, in response to an input signal and to the reference voltages and 2n?I three times cross coupled folding circuits, each of which comprising three differential transistor pairs, said differential transistors pairs being controlled by said control signals and active in a voltage range around a respective one of said reference voltages, with m=3(2??1). In cascade with said 2n?I folding circuits, there are differential transistor pairs in n?1 successive steps 2n?1, 2n—2, 20. To obtain complete folding, switching circuits are provided, cooperating with the transistor pairs in the last 2n?2 steps of the cascade configuration, to supply the respective control signals to those transistors of the respective differential transistor pairs that provide complete folding.

Abstract: The present invention provides a magnetoresistive memory cell (30), comprising a magnetoresistive memory element (31), a first current line (32) and a second current line (33), the first and the second current line (32, 33) crossing each other at a cross-point region but not being in direct contact. According to the invention, a bridging element(34) connects the first and second current lines (32, 33) in the vicinity of the cross-point region. The bridging element (34) is magnetically couplable to the magnetoresistive memory element (31). An advantage of the MRAM architecture according to the present invention is that it allows lower power consumption than prior art devices and high selectivity during writing. The present invention also provides a method of writing a value in a matrix of magnetoresistive memory cells (30) according to the present invention, and a method of manufacturing such magnetoresistive memory cells (30).

Abstract: A method for processing an input burst signal comprising a first step for identifying an additive DC component and generating an output signal, which is representative for an estimated value of said DC component. The method further comprises a second step for detecting a predetermined signal portion from a plurality of possible signal portions included in the input burst signal and generating a control signal indicating the presence of the predetermined signal portion in the input burst signal. The method is characterized in that the first step and the second step are performed in parallel i.e. in a commonly defined time interval from a starting time of the burst.

Abstract: A communication apparatus includes a mechanism for preventing demodulation of text telephone information during reception of a poor quality signal. In one embodiment, the communication apparatus includes a receiver including a demodulator unit configured to receive a signal including a plurality of text telephone symbols. The demodulator unit may be configured to generate a soft decision based upon a frequency and an energy value of each received text telephone symbol. The demodulator unit may be configured to receive a notification that indicates the signal is unusable. In response to receiving the notification, the demodulator unit may be further configured to generate predetermined information that is independent of the plurality of text telephone symbols.