Abstract: The invention relates to a bus system comprising a first station and a second station coupled by a bus for transferring signals. The bus is arranged to operate according to a protocol in which said first station repeatedly sends requests for data to the second station. The protocol comprises a first mode for transferring the requests in a first request format at a first communication speed and at least a second mode for transferring said requests in a second request format at a second speed. The second station is arranged to receive requests in a mode selected from a group of modes comprising said first and second modes, and is arranged to give a first indication to said first station if it is arranged to operate according to the first mode and a second indication if it is arranged to operate according to the second mode. The first station comprises a processor, a controller, and a translator. The processor is operable to generate request properties for requests in the first request format.

Abstract: A plurality of methods, computer program product, and apparatus that use a lower 32 bit field of a 64-bit 802.11 TSF timer, so as to encode the reference time instant without the ambiguity as to whether there the reference time is referring to a future time or a past time. According to an aspect of the present invention, the fact that the low order 32 bits of the TSF timer wraps over in about 71 minutes is exploited to remove any ambiguity in the reference times contained in the Schedule Element frame. One method employs an algorithm base on distance between two reference points to determine whether the timer has wrapped around a time period, and another method uses a delay interval or a timeout to determine whether or not the TSF timer is wrapped or unwrapped. Another method includes determining whether an absolute value of X?O is less than, or greater than or equal to maximum value M/2.

Abstract: An amplifier circuit (100) includes a driver stage ( ) 120 with at least an active device (140) for pre-amplification and output of a pre-amplified signal; and an output stage (160) with at least an active device (180) for further amplification of the pre-amplified signal and output of an amplified signal. A phase shifter (155) shifts the phase of the pre-amplified signal. A detector (190) measures levels of forward and reflected parts of the amplified signal, and a gain and phase control circuit (145) independently and selectively controls and adjusts the phase shifter (155) for optimal amplifier performance and minimal difference between the forward and reflected signals. The gain and phase control circuit also independently and selectively controls and modifies the gain of the active devices (140, 180) of the driver and output stages (120, 160) as a function of the levels of the forward and reflected signals to substantially maintain constant linearity of the amplifier circuit (100) with load variations.

Abstract: In a method of determining the region of interest in images of skin impressions, the skin having ridges and valleys and the images taking the form of image data, values within a first value range being assigned to the ridges and values within a second value range of the image data being assigned to the valleys, the values of the overall image are shifted in the direction of the first value range. The overall image is split into tiles. Mean values of the shifted values for the individual tiles are compared with a reference value. Those tiles whose mean value deviates relative to the reference value in the direction of the first value range are considered at least on a preliminary basis as belonging to the region of interest.

Abstract: A bondwire decoupling filter 300 for filtering RF noise from a transceiver bus 330 of a transceiver 303 connected a device 302 to be protected from RF noise. The filter includes an external capacitor 315 adapted to receive an output from a device 302 to be protected from the RF noise; a first pair of bondwires 305, 307 each having respective first and second ends, and the first pair of bondwires is connected to the external capacitor 315 at respective first ends. A first bondwire 307 of the first pair of bondwires 305, 307 is connected to an output of a voltage regulator 302, and a second bondwire 305 of said first pair of bondwires being connected to the transceiver bus 330 at respective second ends. A second pair of bondwires 310, 312 each having respective first and second ends, are connected to a ground at respective first ends, and connected respectively to a voltage regulator 302 and a transceiver bus 330 at respective second ends.

Abstract: A nonvolatile memory array includes a grid of word lines WL1, . . . ,WL6 and bit lines BL1, . . . ,BL8. Of a plurality of memory cells 210, each memory cell is located at an intersection region of one of the word lines and one of the bit lines. A read/write circuit 280 for reading/writing a data word including a plurality of bits is operative to map each pair of sequential bits of the data word to a respective pair of memory cells located at intersection regions of both a different word line and a different bit line.

Abstract: The invention relates a method for testing a batch of electrical components like Integrated Circuits, the method involving applying a first test (6) on each electrical component from the batch; and applying a second test (12) on electrical components that have failed the first test (6). Advantageously, the second test (12) is applied directly after the first test (6). Preferably, the first test (6) includes a functional test, and the second test (12) includes a Contact-and-Short-Circuit test.

Abstract: The transducer (1) comprises an electrically conductive resonator element (20) extending in a longitudinal direction having a length (l). It can be elastically deformed by an electrically conductive actuator (30) such that the elastic deformation comprises a change of the length (dl). The resonator element (20) is electrically connected to a first contact area (25) and a second contact area (26) thereby constituting a circuit In this circuit the resonator element (20) constitutes a resistor with an ohmic resistance (R) which is a function of the length (l+dl). The transducer (1) further comprises a measurement point (28) electrically connected to the circuit for providing an electrical signal which is a function of the resistance (R).

Abstract: A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a plurality of bus masters coupled to a shared bus. A bus arbiter is provided for arbitrating between requests to access the bus by a first bus master and one or more other bus masters. Accesses by the one or more other bus masters to the bus are restricted in response to a signal indicative of a change in a mode of operation of the RF circuit. In one particular implementation, a communication apparatus employs time domain isolation wherein the digital processing circuit may be placed in a shutdown mode when the radio frequency circuit is active.

Abstract: In a method of encoding lines in a print from the skin and particularly a fingerprint, one line at a time is encoded by means of vertices, which include the starting point and the end point, that are situated on the line, in which case segments of connecting line between adjacent vertices are no more than a preset distance away from the line.

Abstract: A method and arrangement of reducing inter-symbol interference occurring at the digital to analog conversion of a one bit digital signal is provided. During the generation of the one-bit digital signal in a sigma-delta converter the edge-density of the digital signal is measured, the result of the measurement is multiplied with the digital signal and the result of the multiplication is added to the input of the quantizer generating the digital signal. The invention also covers storage media comprising a one-bit digital signal generated in accordance with the invention.

Abstract: An integrated circuit device has boundary scan structure coupled between a test input and the test output. The test register structure is used to shift information from the test input to a test output. The test shift register structure contains a data shift part coupled to connections for a functional circuit under test. In parallel with the data shift part is an instruction shift structure. By means of test control signals it is controlled whether instruction information travels from the test input to the test output through the instruction shift part or through the data shift part. The instruction shift part controls operation of the device in a test mode. A sensor is provided for sensing a physical operating parameter of the device. The sensor has an output coupled to the shift register structure for feeding a sensing result to the test output from the instruction shift part.

Abstract: A wrapper architecture has a parent core A and a child core B. The parent core A comprises scan chains (70), wrapper input cells (71), wrapper output cells (74) and a parent TAM, PTAM [0:2]. Likewise, the child core comprises scan chains (76), wrapper input cells (75) and wrapper output cells (72), and is connected to a child TAM, CTAM [0:2]. Each wrapper input cell (75) and each wrapper output cell (72) of the child core is adapted to be connected to the parent TAM, PTAM, in addition to being connected to the child TAM, CTAM, thereby enabling the child core to be placed in the In-test and Ex-test modes at the same time, and allowing the parent and child cores to be tested in parallel.

Abstract: An apparatus for testing an integrated circuit is disclosed. The apparatus includes a compactor to compress test responses from a circuit under test that is part of an integrated circuit.

Abstract: In a data carrier (1) that is arranged to receive a signal (S) in a non-contacting manner, there is provided a circuit (2) that is arranged, by using the signal (S), to generate a supply voltage (V) for parts of the circuit (2), the circuit (2) having a storage stage (5) that is arranged to store information capacitively, the information being represented by a value of an information voltage (UI) arising at the storage stage (5), and the circuit (2) having an information-voltage generating stage (6) that is arranged to receive a control signal (CS), which control signal (CS) is of a voltage value that is at most equal to the value of the supply voltage (V), and that is arranged to generate the information voltage (UI) by using the control signal (CS), wherein the information-voltage generating stage (6) has a voltage-raising stage (8) that is arranged to raise the value of the voltage of the control signal (CS).

Abstract: An apparatus, program product and method for rotating image data using a block-based approach, wherein for each of a plurality of blocks of image data that define an image, a translation vector is applied to the block to translate the block a desired angle of rotation about a rotation point, e.g., to translate an anchor position for the block from a source point to a destination point. In addition, the image data within the block is rotated according to the desired angle of rotation, such that when the rotated image data is stored at the destination point of the block, the image data within the block is effectively rotated to the desired position.

Abstract: A time discrete filter comprises a sampling rate converter provided with an input and an output, and a down-sampler having a down-sampling factor nd. The time discrete filter further comprises an up-sampler having an up-sampling factor nu, whereby the up-sampler is coupled to the converter input, and the converter output is coupled to the down-sampler. It has been found that if a sampling rate conversion operation is preceded by an up-sampling operation and only after the conversion is followed by a down-sampling operation to a wanted sampling frequency, that then the complexity in terms of the ultimate number of calculations, in particular multiplications and additions, is reduced. This leads to a decrease of the number of instructions per second which is a measure for the complexity of a Digital Signal Processing (DSP) algorithm.

Abstract: Polyphase filters comprise a plurality of filters each filter having passive elements. The filters are provided with integrators comprising amplifiers with admittance elements in feedback paths to create one or more other poles not situated on the negative imaginary axis in the plane-zero plot. A conductance element couples an output of an integrator of the integrators to an input of a previous integrator for introducing a frequency shift for at least one pole in the plane pole-zero plot. A capacitor couples an output of the integrator to an input of a next integrator for improving the quality factor of the polyphase filter. A signal inversion allows conductance elements to have negative values necessary for locating at least one pole at the most optimal location in the plane pole-zero plot.

Abstract: Variable length instructions are formed for execution in a processing system. Each instruction includes a parameter portion having one or more of predetermined types of parameters and an opcode portion. The opcode portion specifies an operation to be performed, the number of parameters in the instruction, and definitive characteristics of the parameters. The parameters may represent data which is compressible, thereby enabling the size of parameters in an instruction to be reduced.

Abstract: Receivers (1) comprising television and radio inputs (11,12) for receiving television and radio signals and comprising switching circuits (2) with two first switches (21,22) to be activated in a first mode and located parallelly to the television input (11) and with two second switches (23,24) to be activated in a second mode and located anti-serially to the radio input (12), and control circuits (3) for controlling the switching circuits (2) are modified in such a way that strong radio signals can no longer disturb the television signals. Thereby one of the first switches (21) and one of the second switches (23) together isolate the inputs (11,12) from each other, and the control circuit (3) supplies a first control signal to the first switches (21,22) and supplies a second control signal to non-common points of the anti-serial second switches (23,24). This kind of receivers (1) no longer need different switching circuits (2) for shielded radio inputs and unshielded radio inputs.