Abstract: A detection circuit for detecting the output power of a power amplifier comprises a first current minor transistor (Ti 1) having a base, which is connectable to a power transistor (T10), and a collector, a RF detection means (RF-det) for detecting the RF current flowing through the current mirror transistor (T11). Said RF detection means (RFdet) is connected to the collector of said first current mirror transistor (T11). Said detection circuit further comprises a biasing means (bias-RF-det) for biasing said RF detection means (RF-det), wherein said biasing means is connected to said collector of said first current mirror (T11) and said RF detection means (RF-det).

Abstract: Voltage controlled oscillator comprising a LC tank circuit (L, C, R) coupled to modulator means and characterized in that the modulator means are coupled to amplifier means via an adder for generating a quadrature periodical output signal having a frequency in a relative wide range, the frequency being controlled by a control signal (V.sub.T) provided to the modulator means.

Abstract: Ballast circuit for operating a gas discharge lamp, comprising a half-bridge DC-AC converter having a voltage controlled oscillator (VCO) for alternately switching the switches (T1; T2) of said half-bridge, said oscillator (VCO) having an input with a control voltage (V vco) which determines the operating frequency of said half-bridge, a resonance circuit connected to said half-bridge for feeding the lamp, and a feedback circuit connected at a first end to said resonance circuit for adjusting the operating frequency of said half-bridge, wherein the other end of said feedback circuit is connected to the input of said voltage controlled oscillator (VCO) and designed such that during at least a substantial part of the start-up period of the lamp an equilibrium exists wherein the half-bridge frequency is at least nearly equal to the resonance frequency and the half-bridge voltage is forced to operate at least nearly in phase with the half-bridge current.

Abstract: A sliding bias circuit for dynamically controlling quiescent current flowing through an output transistor of a linear power amplifier operating in an output frequency band, the linear power amplifier comprising a circuit device for generating a bias signal producing a quiescent current flowing through the output transistor of the RF power amplifier, the sliding bias circuit comprising a detector circuit for detecting RF input to the amplifier and generating an output signal tracking the detected RF input, the output signal directly coupled to the circuit device for automatically modifying the bias signal and the quiescent current through the output transistor. In this manner, the quiescent current at the output stage is reduced and optimized for minimum dissipation and optimal linearity at all power output levels.

Abstract: A method, apparatus, and system for converting an input voltage VIN to a digital output. A comparison of VIN with reference voltages in one or more flash-type analog-to-digital (A/D) converters generates the digital output representing VIN. If one A/D converter is used, the A/D converter is non-linear. If more than one A/D converter are used, the A/D converters are each linear.

Abstract: A method and a circuit for producing a fail-safe output signal in case of an open circuit condition of an input pad of a digital circuit unit, comprising a first inverter stage providing a constant switch level; a second inverter stage providing a variable switch level that depends of the signal level of the input pad and comparing the constant switch level of the first inverter stage with the variable switch level of the second stage and providing an output signal at an output terminal thereof if the variable switch level of the second stage is greater than the constant switch level; and an additional circuit clement connected in series with the second inverter for decreasing the switch level of the second inverter stage.

Abstract: An amplifier circuit (1) includes an amplifying transistor (QØ) and a dc bias circuit (2) for biasing the amplifier transistor (QØ) to obtain a conduction angle of at least about 180°. The dc bias circuit (2) includes a self-bias boosting circuit which has a Wilson current-mirror (Q4, Q5, Q6) integrated with a cascode current-mirror circuit (Q2, Q3) to form an extended Wilson current-mirror circuit (Q2-Q6) having an output coupled to a control terminal of the amplifying transistor (QØ) by a resistor (R1), and a capacitor (C2) coupled from the extended Wilson current-mirror circuit (Q2-Q6) to a common terminal (Gnd).

Abstract: A semiconductor integrated circuit includes an inductor formed by a conductive loop that is fabricated on one or more metal layers. The inductor also includes a dielectric region provided adjacent to the conductive loop. The semiconductor integrated circuit may also include a pattern of electrically isolated metallic fill structures formed within the dielectric region.

Abstract: A variable-impedance device is placed in parallel with the input to a variable-gain amplifier, and is controlled so as to provide a substantially constant load impedance to a source. Preferably, the variable-impedance device includes a diode with a variable bias current. This diode bias current is adjusted inversely with the amplifier bias current, such that the parallel sum of the two input path impedances remains approximately constant across a wide range of gain. This variable gain amplifier system is particularly well suited for use in a wireless transmitter, or cellular telephone.

Abstract: In a method of communicating between a communication station (1) and at least one data carrier (2 (DC)) comprising an information data block (IDB) and useful data (UD=N×UDB), an inventorization procedure with successive procedure runs is carried out at least one part of a block region (NKP-IDB) of the identification data block (IDB) not yet known in the communication station (1) and, in addition, specific useful data (n×UDB) are transmitted from each data carrier (2 (DC)) to the communication station (1) in the implementation of the inventorization procedure, such that after termination of the inventorization procedure at least one part of the identification data block (IDB) of each data carrier (2 (DC)) and the associated specific useful data (n×UDB) are known in the communication station (1).

Abstract: To improve a method as well as a circuit arrangement (100) for detecting the ground offset of parts of a network system, more particularly for checking the ground contact between network control units where data are sent and received over at least one bus system so that, on the one hand, prior to a breakdown event already a warning can be obtained in this respect that the state of the ground connection between the control units is no longer optimal but, on the other hand, ground defects are not shown by mistake, there is proposed 'a! that in the idle state at least one bus line provided for receiving data and/or of at least one receiver line (24), after a predefinable first time period has elapsed, the level voltage (14) of this at least one bus line is scanned and compared with at least one predefinable limit or reference potential value, 'b! in that if the limit or reference potential value is exceeded, at least one ground error signal is generated, and 'c! in that in dependence on the fact whether until a

Abstract: The method for determining the thickness of a dielectric layer according to the invention comprises the step of providing an electrically conductive body (11) having a dielectric layer (13) which is separated from the electrically conductive body (11) by at least a further dielectric layer (3) and a surface (15) of which is exposed. Onto the exposed surface (15) an electric charge is deposited, thereby inducing an electric potential difference between the exposed surface (15) and the electrically conductive body (11). An electrical parameter relating to the electric potential difference is determined and a measurement is performed to obtain additional measurement data relating to the thickness of the dielectric layer (13) and/or to the thickness of the further dielectric layer (3). In this way the thickness of the dielectric layer (13) and/or of the further dielectric layer (3) is determined.

Abstract: A semiconductor device, for example a MOSFET or IGBT, includes a region (30, 36, 50) in the drain drift region (14) juxtaposed with its channel-accommodating region (15) and spaced from the drain contact region (14a) by means of an intermediate portion of the drift region. The region comprises alternating stripes (31, 32) of the first and second conductivity types, which stripes extend alongside the channel-accommodating region (15). In a trench gated device the stripes are elongated in a direction perpendicular to the trench walls. In a planar gate device the stripes extend around the periphery of the channel-accommodating region (15) leaving the region near the gate in a direction perpendicular with respect to the gate electrotes. The dimensions and doping levels of the stripes (31, 32) are selected such that region (30, 36, 50) provides a voltage-sustaining space-charge zone when depleted.

Abstract: To refine an electrical or electronic component having at least one discrete or integrated device formed from a wafer, in plate or disk form, of semiconductive or insulating material, the front face of which device has at least one protruding electrode and is encapsulated by at least one front-face encapsulant, the side faces of which device are at least partly encapsulated by at least one side-face encapsulant, and the rear face of which device is encapsulated by at least one rear-face encapsulant, and to refine a method of producing the same, in such a way that, with the aim of widening the possible uses and applications, electrical contact is made not solely with the front face of the device that is to be housed in the plastics package of very small dimensions, it is proposed that both the side-face encapsulant and the rear-face encapsulant be formed at least partly of layers, but with the layers connected, of electrically conductive material.

Abstract: Consistent with an example embodiment, an electronic device comprises an integrated circuit and a carrier substrate with a bottom and top conductive layer, and is provided with voltage supply, ground and signal transmission connections. In order to enable the use of more than one supply voltage, the integrated circuit is subdivided into core functionality and peripheral functionality, and the carrier substrate is subdivided into a corresponding core area and peripheral area. The ground connections of both core and periphery are mutually coupled through an interconnect in the carrier substrate. This interconnect is particularly a ground plane, and allows the provision of a transmission line character to the interconnects for signal transmission of the periphery.

Abstract: The present invention relates to magnetic or magnetoresistive random access memories (MRAMs). The present invention provides an array with magnetoresistive memory cells arranged in logically organized rows and columns, each memory cell including a magnetoresistive element (32A, 32B). The matrix comprises a set of column lines (34), a column line (34) being cells of a column. A column line (34) is shared by two adjacent columns, the shared column line (34) having an area which extends a continuous conductive strip which is magnetically couplable to the magnetoresistive element (32A, 32B) of each of the memory cells of a column. A column line (34) is shared by two adjacent columns, the shared column line (34) having an area which extends over substantially the magnetoresistive elements of the two adjacent columns sharing that column line.

Abstract: The carrier (30) comprises a first etch mask (14), a first metal layer (11), an intermediate layer (12), a second metal layer (13) and a second etch mask (17). Both the first and the second etch mask (14, 17) can be provided in one step by means of electrochemical plating. After the first metal layer (11) and the intermediate layer (12) have been patterned through the first etch mask (14), an electric element (20) can be suitably attached to the carrier (30) using conductive means. In this patterning operation, the intermediate layer (12) is etched further so as to create underetching below the first metal layer (11). After the provision of an encapsulation (40), the second metal layer (13) is patterned through the second etch mask (17). In this manner, a solderable device (10) is obtained without a photolithographic step during the assembly process.

Abstract: A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a first timing circuit that provides timed signals to control timing of system operations during an active mode of operation of the digital processing circuit, and a second timing circuit that provides timing signals to control timing of system operations during an active mode of operation of the radio frequency circuit. In one particular embodiment, at least a portion of the first timing circuit is disabled when the radio frequency circuit is active (receiving and/or transmitting).

Abstract: A description is given of an arrangement for determining the position of a magnetic-field-sensitive sensor unit in the magnetic field of a magnet arrangement having an at least substantially bar-shaped contour along an at least substantially rectilinear motion coordinate that extends parallel to a longitudinal axis of the at least substantially bar-shaped contour, in which the magnetic-field-sensitive sensor unit is intended to measure a component of the magnetic field which extends in a plane that is at least substantially parallel to the longitudinal axis of the at least substantially bar-shaped contour in a manner at least substantially perpendicular to this longitudinal axis, and the magnet arrangement has a magnetic north pole in the region of a first end of the at least substantially bar-shaped contour, a magnetic south pole in the region of a second end of the at least substantially bar-shaped contour, and a narrowing of the at least substantially bar-shaped contour in the central region extending betw

Abstract: A DC-DC converter includes a switch (S1) which periodically connects an inductor (L) to a DC-input voltage (Vi) during an on-period (Ton) of a period time (Tp). The operating frequency (fo) of the DC-DC converter is the inverse of the period time (Tp). An output (O1) of the DC-DC converter is coupled to the inductor (L) to supply an output voltage (Vo). A controller (CO) controls the operating frequency (fo) of the DC-DC converter to be substantially proportional to the output voltage (Vo) to obtain a substantially constant average duration of the on-period (Ton) as function of the output voltage (Vo).