Abstract: A refrigerant management system provides for optimal compressor performance by providing a compressor motor designed to operate at peak efficiency under a first cooling load and at least one sensor for generating a signal that indicates the actual cooling load. A controller is provided that determines any difference between the first cooling load and the actual cooling load from the sensor signal data. The controller is coupled to a refrigerant storage device to either add or remove refrigerant to maintain the system at or near the first cooling load in accordance with the signal form the first sensor indicating the actual cooling load. Consequently, the present invention provides for automatic adjustment of the amount of refrigerant in a cooling loop system to maintain a predetermined cooling load that allows operate a compressor motor to operate at its peak efficiency.

Abstract: An operating system architecture is disclosed. The operating system architecture is configured to provide a user space and a kernel space. The operating system architecture comprises a number of tasks, a message, and a microkernel. The tasks are executed in the user space, while the microkernel is executed in the kernel space. The microkernel supports an application programming interface (API) that is configured to support a limited number of directives, the limited number of directives being substantially fewer in number than a number of directives supported by an application programming interface of a traditional operating system. The microkernel is configured to pass the message from a first one of the tasks to a second one of the tasks by virtue of the application programming interface being configured to support message-passing directives.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: Rotated-read register file and CAM array memory structures include corruption prevention circuits that are used to force a read bit line to a known digital value when a cell structure is being written to at the same time a read is performed on the corresponding read word line. Consequently, according to the present invention, the value on the read bit line is forced to a known digital value by the corruption prevention circuit of the invention and the prior art problem of the value being read having an unknown or indeterminate value that is neither a digital low nor a digital high is eliminated. Therefore, using the method and structure of the invention, indeterminate values are never propagated down stream to the sensing elements, logic elements, or other downstream circuitry of the system and there is no potential failure of the downstream circuitry.

Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

Abstract: A method and apparatus for sharing resources in a network environment. An application running on a client can access a resource on a remote computer by submitting a request via an Internet browser. The request is analyzed, converted to proper format and is transferred over the network lines to a server that can satisfy the request. For security reasons, an application may not be authorized to submit a request directly to a server on the Internet. If a requesting application has a trusted status, then its request for connecting to the server is granted. If a request submitted by an application to a server is denied, then a server that entrusts the application is identified, and the request is submitted to that server. A program code called a “servlet” is implemented on that server to accept the requests submitted by a trusted application. The submitted requests are analyzed by the servlet and are forwarded to a resource server that can satisfy the requests.

Abstract: Clocked half-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a half-rail differential logic circuit with shut-off that does not experience the large or “dip” experienced by prior art half-rail differential logic circuits and is therefore more power efficient.

Abstract: A method and structure for supply gating low power electronic components uses low threshold gating transistors. The low power components operate at supply voltages of less than one volt and typically in the range of 150 to 400 millivolts. Using low threshold gating transistors, the leakage current of the devices, and therefore the standby power dissipation, can be minimized by using any one, or a combination of, four methods including: overdriving the low threshold gating transistors on; overdriving the low threshold gating transistors off; combining very low threshold device transistors with low threshold gating transistors; and providing the low threshold gating transistors with back bias.

Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

Abstract: Method and apparatus for locking by sharing lock states. Each resource is associated with a lock state that represents its lock. Lock states are made of one set of transactions per locking mode. Resources may share the same lock state if the state of their respective locks is equal. Locking operations change the association between a resource and a lock state to reflect changes to the resource's lock.

Abstract: Clocked full-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the large “dip” experienced by prior art full-rail differential logic circuits and is therefore more power efficient.

Abstract: Clocked half-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a half-rail differential logic circuit with shut-off that does not experience the large or “dip” experienced by prior art half-rail differential logic circuits and is therefore more power efficient.

Abstract: Clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention do not include complementary logic elements. According to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output. In addition, the clocked half-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic block to provide a driver function.

Abstract: Clocked full-rail differential logic circuits with shut-off include a shut-off device. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the “dip” experienced by prior art full-rail differential logic circuits and is therefore more power efficient. In addition, the present invention provides a full-rail differential logic circuit with shut-off that is more resistant to noise than prior art full-rail differential logic circuits.

Abstract: An embodiment consistent with the present invention includes a method and apparatus for forming a multicast repair tree. The methods perform by a data processor and comprises the steps of determining, for each of a plurality of potential heads in a multicast group, a ranking value associated with the potential head; advertising, by the potential heads to a plurality of potential receivers; prioritizing, by a potential receiver, the ranking values from the potential heads; and binding, by a potential receiver to the head having the highest ranking value, thereby forming a group of which the potential receiver,is a member and the potential head is the head. The ranking values may include “able”, “unable”, “willing”, and “reluctant.” The ranking value of a potential head determines in accordance with a static or a dynamic configuration. Ranking values determine dynamically based on ranges of system resource levels such as memory and available processor resources.

Abstract: A method and apparatus that ensures that requests for pages in a particular domain name are routed to the same proxy server by all of a plurality of clients. If, for example, a proxy server has a persistent connection to a server for a domain, all incoming requests for that domain will be sent to the proxy server and will, thus, will be able to take advantage of the persistent connection. Each client contains a proxy table that is periodically updated by one or more of the proxy servers. A proxy table in a client contains an entry corresponding to each proxy server. When a client needs to access a resource through a proxy server, the client truncates the address (e.g., the URL) of the resource. Thus, for example, all addresses in a particular domain name are truncated to the same value. The truncated address is then used to hash into the proxy table in the client and to identify a proxy server. The client sends its request to the identified proxy server.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic block to provide a driver function. Consequently, the clocked half-rail differential logic with amplifier circuits of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art half-rail differential logic circuits.

Abstract: A series of secondary or “shadow” storage elements are employed that duplicate, or “shadow”, the information in a circuit's core logic shadowed functional registers. These shadow storage elements are then coupled to form a separate, independently-addressable shadow scan path. The information contained in the shadowed functional registers of a circuit is then shifted out via the shadow scan path without altering the shadowed functional registers using special commands issued from a JTAG controller.

Abstract: Clocked full-rail differential logic circuits with sense amplifier and single-rail logic are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. In Addition, according to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output. Consequently, the clocked full-rail differential logic circuits with sense amplifier and single-rail logic of the invention are smaller, less complex and are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits.