Abstract: The present invention is a universal secure token scheme that provides two way authentication, credit, debit, and stored value operations. The invention permits the use of universally available networks to access corporate, private, and proprietary devices. The invention provides strong authentication, offers optional encryption of the established session, and operates without requiring special permission to reconfigure firewalls. One application of the invention provides a universal token scheme that can be used in debit and stored value transactions. In one embodiment, devices and services are treated as URLs and a smart card is configured to perform the necessary HTTP protocol to access the URL.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. The addition of the sense amplifier circuit, and second delayed clock signal, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic block to provide a driver function. Consequently, the clocked half-rail differential logic circuits of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art half-rail differential logic circuits.

Abstract: Modified high-speed flip-flop include an evaluation window that is self-adjusting and data selective. Consequently, modified high-speed flip-flop circuits designed according to the invention include an evaluation window that can be longer when the data signal is a digital “1” and significantly shorter when the data signal is a digital “0”. Therefore, the evaluation window of the modified high-speed flip-flop circuits of the invention selectively varies according to the state of the data signal so there is minimal hold time, increased efficiency and no opportunity for the creation of a racing condition. Consequently, the modified high-speed flip-flops of the invention are more robust and more efficient than prior art flip-flops.

Abstract: Clocked half-rail differential logic circuits with single-rail logic of the invention do not include complementary logic elements. According to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output OUTBAR. Consequently, clocked half-rail differential logic circuits with single-rail logic of the invention use less power and, therefore, generate less heat, require less space, and are simpler in design so that they are more flexible, more space efficient and more reliable than prior art half-rail differential logic circuits.

Abstract: One embodiment of the invention provides a method and apparatus for remotely managing data in a network system comprising at least one mobile device (e.g. a PDA, cellular phone, two-way pager, or mobile computer) and a least one server computer connected via an interconnection fabric, wherein the mobile device is registered with the server and configured to issue commands to a bot service using electronic mail messages or some other viable data transmission mechanism. The bot service responds to the commands by interfacing with the server computer to perform the requested action on behalf of the mobile device.

Abstract: Clocked full-rail differential logic circuits are provided with shut-off devices. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the large pre-charge high or “dip” experienced by prior art full-rail differential logic circuits and is therefore more power efficient. In addition, the present invention provides a full-rail differential logic circuit with shut-off that is more resistant to noise than prior art full-rail differential logic circuits.

Abstract: A method for forming an image sensor assembly includes forming a lead frame or Land Grid Array (LGA) integrally into a molded image sensor die package so that the lead frame or LGA is fully supported and structurally fortified by the molded image sensor die package. An image sensor die is then attached to the thus supported lead frame or LGA using a standard flip-chip connection.

Abstract: A method for determining the setup and hold times of static flip-flops during the design and development of integrated circuits. The method utilizes simulations of an integrated circuit to determine a first amount of time required for a data signal to be transmitted from a first external node to a predetermined node in the register of a static flip-flop, and a second amount of time required for a clock signal to be transmitted from a second external node to the predetermined node. The setup time is determined by calculating a difference between the first amount of time from the second amount of time. Similarly, a hold time for the flip-flop is determined by calculating a difference between the amounts of time required for data and the clock signal to reach a second predetermined internal node of the flip-flop.

Abstract: A data structure is disclosed. The data structure includes a data descriptor record. In turn, the data descriptor record includes a type field, a base address field, an offset field, wherein the, and a length field. The type field may be configured, for example, to indicate a data structure type. The data structure type may be configured to assume a values indicating one of a contiguous buffer, a scatter-gather list and a linked list structure, among other such data structures. The base address field may be configured, for example, to store a base address, with the base address being a starting address of a secondary data structure associated with the data descriptor record. The offset field may be configured, for example, to indicate a starting address of data within a secondary data structure pointed to by a base address stored in the base address field.

Abstract: The invention is a method and apparatus for determining an approximate network distance using one or more reference points. In accordance with an embodiment of the invention, the method comprises the steps of selecting at least one reference point positioned along a path between first and second points of a network, generating first distance metric information associated with at least one path associating a first point and the at least one reference point, generating second distance metric information associated with at least one path associating a second point and the at least one reference point, and determining a total approximate distance between the first point and the second point along one or more paths based on the first and second distance metric information.

Abstract: Clocked half-rail differential logic circuits with single-rail logic of the invention do not include complementary logic elements. According to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output OUTBAR. Consequently, clocked half-rail differential logic circuits with single-rail logic of the invention use less power and, therefore, generate less heat, require less space, and are simpler in design so that they are more flexible, more space efficient and more reliable than prior art half-rail differential logic circuits.

Abstract: An improved high-speed domino logic circuit uses two delayed clock signals, CLKD and CLKDBAR, and three transistors to introduce a transition delay time. According to the invention, the delayed clock signals are used in conjunction with the three added transistors to avoid the contest or “fight” between a first node and the keeper transistor in the event of a path to ground being created through the logic block portion of improved high-speed domino logic circuit. The improved high-speed domino logic circuits of the invention, in contrast to prior art domino logic circuits, can be designed to have high noise immunity and increased speed. In addition, since according to the invention, only three new transistors are required, the modification of the invention is space efficient and readily incorporated into existing designs.

Abstract: Clocked full-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock and a shut-off device. The addition of the sense amplifier circuit, and second delayed clock signal allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the differential logic network to provide a driver function. The addition of the shut-off device provides a full-rail differential logic circuit with shut-off that does not experience the large “dip” experienced by prior art full-rail differential logic circuits and is therefore more power efficient.

Abstract: In embodiments of the invention, a method and apparatus for dynamic proxy insertion in network traffic path is described. According to one or more embodiments of the invention, a request and/or response message may be modified to include one or more thru-proxy tags to identify a network (or traffic) node (e.g., a proxy, server, or intermediary). For example, a request directed to a server or a response directed to a client may be altered to insert a plurality of intermediate or final destination designations. In so doing, a path of a request or response may be altered dynamically. A thru-proxy tag in a response may be inserted in a related request to identify a destination or node such that the request is sent to the destination in the thru-proxy tag before being sent to an origin server. Thru-proxy tags may be used to identify multiple and/or alternate destinations.

Abstract: A thermal storage device for maintaining the temperature of an article at a desired temperature for a length of time comprises a compartment within which the article may be positioned, an evaporator which is disposed in heat exchange relation with respect to the compartment, a receiver which is fluidly connected to the evaporator, a sorber which is fluidly connected between the evaporator and the receiver and which includes a sorbent that is capable of adsorbing a refrigerant, a desorbing device for desorbing the refrigerant from the sorbent, and a power connection device for releasably connecting an external power supply to the desorbing device. When the desorbing device is connected to the external power supply, the refrigerant is desorbed from the sorbent and communicated to the receiver.

Abstract: A method and apparatus for compensating for gate current through a first capacitor includes: a biasing circuit; a first compensation transistor; a second compensation transistor; and a compensation capacitor. The biasing circuit ensures the bias voltage across the compensation capacitor is equal to the bias voltage across the first capacitor. In addition, the size of the second compensation transistor is chosen such that if, the ratio of the area of the compensation capacitor divided by the area of the first capacitor is area ratio “AR”, then, the ratio of the size of first compensation transistor divided by the size of second compensation transistor is also area ratio “AR”. As a result, according to the method and apparatus of the present invention, the gate current Ig through the first capacitor is equal to the current drained off through second compensation transistor.

Abstract: A multiple compressor refrigeration heat sink module is suitable for use in standard electronic component environments. The multiple compressor refrigeration heat sink module is self-contained and is specifically designed to have physical dimensions similar to those of a standard air-based cooling system. As a result, the multiple compressor refrigeration heat sink module can be utilized in existing electronic systems without the need for significant system housing modification or the “plumbing” associated with prior art liquid-based cooling systems. The multiple compressor refrigeration heat sink module is also well suited for applications that require a highly reliable, energy and space efficient, cooling systems for electronic components such as multi-chip modules and mainframe computer applications.

Abstract: A multi-level cache and method for operation of a multi-level cache generating multiple cache system accesses simultaneously. Each access request includes an address identifying a memory location having data that is a target of the access. A insertion pointer inserts each access request into an entry in a memory scheduling window. Each entry is marked as valid when that entry is ready to be applied to a first cache level. A picker picks valid entries from the memory scheduling window by pointing to the picked entry and applying the address therein to the first cache level. The picking occurs in a free-running mode regardless of whether the accesses hit in the first cache level. A second cache level, receives accesses that have missed in the first cache level. A resource monitor in the second cache level determines when a predetermined number of resources are committed to servicing the accesses that have missed in the first cache level.

Abstract: A method, apparatus, and computer program product for handling IEEE 754 standard exceptions for Single Instruction Multiple Data (SIMD) instructions. Each SIMD sub-operation's corresponding IEEE 754 exception flag is bit-wise “ORed” with an accrued exception field if a trap enable mask field is configured to mask the exception, with the “ORed” result written back in the accrued exception field. If the trap enable mask field is configured to enable the exception, the accrued exception field and a current exception field are cleared, and an unfinished floating-point exception flag is set in a floating-point trap type field. The actual sub-operation(s) causing the exception is determined through software.

Abstract: A method and apparatus for packaging and distributing software. Embodiments of the invention comprise a software packaging system that is portable across many platforms. Each package is self-contained in form of a single-file entity that comprises a payload file and a control file. The payload file is an archive file that contains a compressed collection of all the software files that are required for installation of the software package. The control file includes the necessary information for installation of the files contained in the payload file, in addition to other descriptive information used to determine the size, type, location of storage, and other useful attributes of a software package, even before it is installed on a system. Security measures have been implemented in the system to detect a package the contents of which have been tampered with. Embodiments of the invention can be utilized to install packaged software that is accessible via the Internet.