Abstract: Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

Abstract: A method for significantly decreasing the number of times prior art coding schemes, such as variable length coding, are implemented in the course of encoding/decoding a given data block includes cataloging the occurrences, or locations, of a designated frequently occurring value in the data block and then excluding the frequently occurring value from the prior art coding scheme.

Abstract: A method and apparatus for efficient and reliable multicasting in a network environment. In embodiments of the invention, a sender transmits identical information encapsulated in data packets to a plurality of receivers. Periodically, receivers submit responses that include control information regarding the loss or receipt of data packets transmitted by the sender. Using these information a sender retransmits any undelivered packets to intended receivers. Responses submitted by the participating receivers, generate a traffic flow that can consume a substantial portion of the network bandwidth. Thus, in embodiments of the invention, the rate at which the responses are submitted is monitored and controlled to minimize control traffic. Over congestion of the network bandwidth with control information is undesirable as it adversely effects the data transmission rate. Thus, in embodiments of the invention, packet loss responses are generated at time intervals.

Abstract: In embodiments of the invention, a method and apparatus for dynamic proxy insertion in network traffic path is described. According to one or more embodiments of the invention, a request and/or response message may be modified to include one or more thru-proxy tags to identify a network (or traffic) node (e.g., a proxy, server, or intermediary). For example, a request directed to a server or a response directed to a client may be altered to insert a plurality of intermediate or final destination designations. In so doing, a path of a request or response may be altered dynamically. A thru-proxy tag in a response may be inserted in a related request to identify a destination or node such that the request is sent to the destination in the thru-proxy tag before being sent to an origin server. Thru-proxy tags may be used to identify multiple and/or alternate destinations.

Abstract: Embodiments of the invention comprise a method and apparatus for avoiding array class creation in, for example, virtual machines for object-oriented programming languages. Embodiments of the invention reduce the internal structures created for arrays at runtime, thereby reducing memory consumption. Unlike in a traditional implementation, where a separate array class is created for each array of different type, in an embodiment of the invention the type information is stored in array instances instead. Array classes are not created at all. Rather, the root class of the class hierarchy (e.g., “java.lang.Object”) is used as the class of each array instance. When an array instance is instantiated, a reference to the “java.lang.Object” class is created in the class field of the array instance and the type information is stored in the instance itself. In one embodiment of the invention, an integer type value is stored in a special type field of the array instance.

Abstract: A method for supply gating low power electronic devices uses low threshold gating transistors. The low power devices operate at supply voltages of less than one volt and typically in the range of 150 to 400 millivolts. Using low threshold gating transistors, the leakage current of the devices, and therefore the standby power dissipation, can be optimized by using any one, or a combination of, four methods including: overdriving the low threshold gating transistors on; overdriving the low threshold gating transistors off; combining very low threshold device transistors with low threshold gating transistors; and providing the low threshold gating transistors with back bias.

Abstract: A method and apparatus for modeling the specular reflection of light from an object is disclosed. In accordance with one embodiment of the method, a portion of the object is modeled by one or more surfaces each having at least one vertex and an edge point corresponding to an edge. A sine value associated with a highlight angle is determined at each vertex and edge point, and a control value is determined at each vertex and edge point using the sine values. A specular input component at each point on the surface is determined using the control values. The specular input component is utilized to determine the specular light component at that particular point. Embodiments of apparatus implementing the method are also disclosed.

Abstract: A memory controller for a memory subsystem of a computer system connects to a processor bus. The memory controller is for use with memory devices such as RDRAM or DDR SDRAM that allow for multiple open pages. Memory references are remapped by an address mapper and processed by a page tracking buffer to keep track of open pages in the memory devices. The controller also has a state machine, and an interface to memory devices. The page tracking buffer has a row address content addressable memory for determining when a reference is in an open page, and a bank content addressable memory for determining when a reference is to the same bank as an open page. The controller closes open pages of a bank prior to opening new pages in that bank. The page tracking buffer has fewer lines than the product of the maximum number of memory devices times the maximum number of simultaneously open pages of each device, but provides for tracking any page of any of the memory devices.

Abstract: An automated method of analyzing crosstalk in a digital logic integrated circuit, the method operating on a digital computer, is described. The method uses available software to make an extracted, parameterized netlist from a layout of the integrated circuit. For at least one potential victim wire of the plurality of wires, determining a subset of the wires of the chip are found to be potential aggressor wires that may couple to the victim wire. The aggressor wires are combined into a common aggressor. A risetime of the common aggressor is calculated and used to calculate the magnitude of coupled noise on the victim wire induced by the aggressor wires. An alarm threshold for each potential victim wire is determined based upon the type of logic gate that receives the victim wire.

Abstract: A method for significantly decreasing the number of times prior art coding schemes, such as variable length coding, are implemented in the course of encoding/decoding a given data block includes cataloging the occurrences, or locations, of a designated frequently occurring value in the data block and then excluding the frequently occurring value from the prior art coding scheme.

Abstract: A method and apparatus for building an integrated circuit. A description of the logical operation of a module in a hardware description language is provided, which includes annotations in the form of design directives. An interpreting process is configured to read the annotations and identify which logical and physical design tools are needed to process each module in the description, as well as the order in which to invoke the logical physical design tools. Dependencies in the execution of the design tools on the various modules of the description are analyzed to determine where the processing of modules may be performed in parallel to optimize execution.

Abstract: An automated method of analyzing crosstalk in a digital logic integrated circuit on a digital computer is described. The method uses available software to make an extracted, parameterized netlist from a layout of the integrated circuit. The netlist has gate and black box invocations as well as transistor invocations. Library models are used to find driving resistances and capacitances associated with the gate and black-box invocations. For at least one potential victim wire of the plurality of wires, a subset of the wires of the chip are found to be potential aggressor wires to the victim wire. The aggressor wires are combined into a common aggressor. A risetime of the common aggressor is calculated and used to calculate the magnitude of coupled noise on the victim wire induced by the aggressor wires. An alarm threshold for each potential victim wire is determined based upon the type of logic gate that receives the victim wire.

Abstract: Programmable logic structures include logic blocks that operate at very low supply voltages. According to the invention, a pass transistor is positioned between logic blocks. Since the logic blocks of the invention operate at very low supply voltages, the pass transistor can be overdriven on, thereby reducing the added resistance. In one embodiment of the invention, the pass transistor is a low threshold transistor. In this embodiment, the pass transistor is also overdriven off to reduce leakage current and further isolate the logic blocks.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: Programmable logic structures include logic blocks that operate at very low supply voltages. According to the invention, a pass transistor is positioned between logic blocks. Since the logic blocks of the invention operate at very low supply voltages, the pass transistor can be overdriven on, thereby reducing the added resistance. In one embodiment of the invention, the pass transistor is a low threshold transistor. In this embodiment, the pass transistor is also overdriven off to reduce leakage current and further isolate the logic blocks.

Abstract: Buried platform wells are specifically used to electrically interact with the platform transistors of the invention. The dopant concentration distribution of the buried platform wells is used to change the threshold voltage of the platform transistors of the invention by introducing a tail dopant concentration into the active region of the platform transistors. The platform transistors of the invention can also be used in conjunction with standard transistors, on a single structure, to provide both low and relatively high threshold voltage transistors on a single structure. Consequently, using the method and structure of the invention, considerable versatility and design flexibility are achieved with minimum additional structural complexity.

Abstract: A method and apparatus for local advertising. Internet Service Providers (ISPs) or proxies owned by an ISP insert advertisements transmitted from a web host to a client. The advertisement may be stored in the proxy's cache or may be retrieved from a web server for an advertiser. By providing the ISP with the ability to insert the advertisement, advertisements appear on small web sites that do not normally attract advertisers. Additionally, due to the number of advertisements placed by an ISP, small advertisers may have their advertisement appear in connection with frequently used web sites. One or more embodiments of the invention provide for an ISP to collect and store demographic information such as the user's age, residence, credit history, etc. Additionally, stored information may include web sites the user has accessed, time spent on each web site, and any searches performed by the user.

Abstract: A device for performing a consecutive clear bits count on an operand with an offset includes a plurality of logic circuits, each associated with a prioritized portion of the operand. Each logic circuit activates an all-zero signal when its respective portion of the operand consists of all zeros, performs a leading zero count on its respective portion of the operand, and generates a leading zero signal by offsetting its leading zero count with a first portion of the offset. Also, a priority encoder generates a signal encoding the priority of the highest priority inactive all-zero signal, and muxes select first and second portions of the leading zero signal associated with the highest priority inactive all-zero signal as a first portion of the consecutive clear bits count and a carryout selector signal, respectively, in accordance with the priority encoded signal.

Abstract: Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and voltage scalability of the latches of the invention is further increased by designing latches with uniform stack height components. One embodiment of the invention allows for minimum supply voltages of 60 millivolts, an improvement of over thirteen hundred percent compared with the typical prior art minimum voltage requirement of 800 millivolts.

Abstract: A structure including volatile memory devices that are used by the host computer system as the storage media. The volatile memory devices include volatile memory device back up systems to provide power to both the volatile memory and non-volatile memory in the event of power failure. The volatile memory devices also connect directly to an expansion bus of the host computer system, such as a PCI bus. Therefore, the volatile memory devices of the invention include a high-speed path to the host computer system and the volatile memory devices of the invention are faster than prior art devices, use less power and are lower cost.