Patents Represented by Attorney, Agent or Law Firm Piper Rudnick
  • Patent number: 7033801
    Abstract: A method of generating a double stranded (ds) recombinant nucleic acid molecule covalently linked in both strands by contacting two or more ds nucleotide sequences with a topoisomerase under conditions such that both termini of at least one end of a first ds nucleotide sequence are covalently linked by the topoisomerase to both termini of at least one end of a second ds nucleotide sequence is provided. Also provided is a method for generating a ds recombinant nucleic acid molecule covalently linked in one strand, by contacting two or more ds nucleotide sequences with a type IA topoisomerase under conditions such that one strand, but not both strands, of one or both ends of a first ds nucleotide sequence are covalently linked by the topoisomerase. Compositions for performing such methods, and compositions generated from such methods also are provided, as are kits containing components useful for conveniently practicing the methods.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: April 25, 2006
    Assignee: Invitrogen Corporation
    Inventors: John Carrino, James Fan, Robert P. Bennett, Jonathan D. Chesnut, Martin A. Gleeson, Knut R. Madden
  • Patent number: 7035151
    Abstract: Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: April 25, 2006
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Sakhawat M. Khan, George J. Korsh
  • Patent number: 7035906
    Abstract: This invention generally relates to one or more computer networks having computers like personal computers or network servers with microprocessors linked by broadband transmission means and having hardware, software, firmware, and other means such that at least one parallel processing operation occurs that involve at least two computers in the network. More particularly, this invention relates to one or more large networks composed of smaller networks and large numbers of computers connected, like the Internet, wherein more than one separate parallel processing operation involving more than one different set of computers occurs simultaneously and wherein ongoing processing linkages can be established between virtually any microprocessors of separate computers connected to the network.
    Type: Grant
    Filed: May 16, 2000
    Date of Patent: April 25, 2006
    Inventor: Frampton E. Ellis, III
  • Patent number: 7034014
    Abstract: The present invention relates to phosphonate compounds, compositions containing them, processes for obtaining them, and their use for treating a variety of medical disorders, e.g., osteoporosis and other disorders of bone metabolism, cancer, viral infections, and the like.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: April 25, 2006
    Assignee: The Regents of the University of California
    Inventors: Karl Y. Hostetler, James R. Beadle, Ganesh D. Kini
  • Patent number: 7031977
    Abstract: A hierarchical set of records has multiple hierarchical levels and depths. Each of the records has a tag that is unique within the hierarchical set of records. A method for retrieving a record includes identifying one of the records in the hierarchical set and modifying the tag, thereby producing a key. The hierarchical set of records is indexed only once. A record is selected and retrieved based on the indexing which applies the key to the hierarchical set of the records.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: April 18, 2006
    Assignee: Plumtree Software, Inc.
    Inventors: Kurt Frieden, Prasanna Srikhanta
  • Patent number: 7030658
    Abstract: Systems and methods for reducing the power consumption of some combinations of logic gates by reducing the number of unnecessary transitions that are made by logic gates that do not affect the output of the logic. In one embodiment, a modified exclusive-OR (XOR) gate is coupled to a modified multiplexer. The XOR gate has two inputs, Ain and Bin, and an output, XORout, which is provided as an input to the multiplexer. Another input to the multiplexer is Cin. A select signal is input to the multiplexer to select either Cin or XORout to be provided at the output of the multiplexer. If XORout is selected, the XOR gate operates in a first mode in which it functions as a normal XOR gate. If Cin is selected, the XOR gate operates in a second mode in which the XOR gate uses less power than when the XOR gate operates normally.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: April 18, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Murakami, Osamu Takahashi, Jieming Qi
  • Patent number: 7032191
    Abstract: A system for integrated circuit (IC) design. A structural multi-project wafer (SMPW) comprises a plurality of pre-manufactured and pre-validated functional blocks. The SMPW is pre-fabricated up to a contact layer so that a user can customize and program different blocks of the SMPW to the user's requirements. An SMPW provider maintains an inventory of SMPWs. If one of the SMPWs can meet all of a user's IC design requirements, or can serve an intermediate step in a user's IC design process, such as market/concept validation or IP validation, the SMPW is provided to the user. The user can then proceed directly to production using a streamlined design flow having a very short cycle time of 1–3 months. Otherwise, the user proceeds to production using a normal design flow having a much longer cycle time.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: April 18, 2006
    Assignee: Rapid Bridge LLC
    Inventors: Behnam Malekkhosravi, Daniel J. Woodard
  • Patent number: 7032064
    Abstract: A single chip embedded microcontroller has a processor that communicates with multiple non-volatile erasable PROMS which may be an OTPROM and an EEPROM. The processor also communicates with a high voltage generator that produces the erase and write voltages for the OTPROM and EEPROM. A switch communicates with the high voltage generator and switches the erase and write voltages alternately between the OTPROM and EEPROM. The OTPROM and EEPROM are FLASH arrays. The FLASH array technology allows the EEPROM and OTPROM to have similar erase and write voltages and therefore to share one high voltage generator. The high voltage generator is switched alternately between the first and second non-volatile erasable PROM arrays to enforce the principle that the EEPROM and OTPROM cannot be written to or erased at the same and may only be written to or erased one at a time.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: April 18, 2006
    Assignee: Emosyn America, Inc.
    Inventors: Philip C. Barnett, David Sowards
  • Patent number: 7031214
    Abstract: A digital multibit non-volatile memory integrated system includes autozero multistage sensing. One stage may provide local sensing with autozero. Another stage may provide global sensing with autozero. A twisted bitline may be used for array arrangement. Segment reference may be used for each segment. The system may read data cells using a current sensing one or two step binary search. The system may use inverse voltage mode or inverse current mode sensing. The system may use no current multilevel sensing. The system may use memory cell replica sensing. The system may use dynamic sensing. The system may use built-in byte redundancy. Sense amplifiers capable of sub-volt (<<1V) sensing are described.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: April 18, 2006
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Hieu Van Tran
  • Patent number: 7028878
    Abstract: A mechanical stapling device for fastening deep tissue during the closing of peritoneal side of a stab wound, which is associated with a laparoscopic surgical procedure, is provided. Also provided is a unique staple for use with the stapling device of the present invention. A method of using the device and staple of the present invention is also provided.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: April 18, 2006
    Inventor: William Bauer
  • Patent number: 7025675
    Abstract: A server-based video game system maintains a number of video game characters having computer-simulated genetic (“digenetic”) structures that prescribe a number of physical and cognitive performance traits and characteristics for the video game characters. The system allows end users to establish remote online access to the game characters (via, e.g., the Internet). The results of competitions and training activities are based upon the game characters' digenetics, the conditions of the game environment, and the game characters' current levels of physical and cognitive development. The game characters' performance capabilities and cognition are updated continuously in response to the results of competitions and training activities. Competition and training results can be processed by the game servers and transmitted to the end user presentation devices for graphics rendering. In this manner, the video game system need not be burdened by network latency and other delays.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: April 11, 2006
    Assignee: Digenetics, Inc.
    Inventors: David B. Fogel, Timothy J. Hays, Douglas R. Johnson, Thomas P. Lang, Jr.
  • Patent number: 7027348
    Abstract: An integrated circuit memory device has a plurality of memory cells arranged in a plurality of arrays. Each array has a plurality of rows, and a plurality of column lines, and a plurality of row lines connecting to the memory cells in each array. The memory cell in an array is addressable by a column line and a row line. A column address decoder receives a column address signal and selects one or more column lines of each array in response. A row address decoder receives a row address signal and selects a row line of each array in response. The memory device also has a plurality (k) of sense amplifiers, with one sense amplifier associated with each array, connectable to one or more column lines of the array and receives a signal therefrom supplied from an addressed memory cell. The memory device further has a register; and a control circuit.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: April 11, 2006
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Neal Berger, George Chia-Jung Chang, Pearl Po-Yee Cheng, Anne Pao-Ling Koh
  • Patent number: 7027996
    Abstract: A method for automatically planning is provided, comprising the steps of receiving a plurality of tasks that a user needs to perform, each task having an earliest start time, a latest stop time, a duration for completing the event and a reward value for completing the event, the tasks including a fixed task having the duration being equal to the time period between the earliest start time and the latest stop time and a floating task having a duration that is less than the time period between the earliest start time and the latest stop time, arranging said fixed task into a plan for the user based on the earliest start time, duration and reward of the fixed task, determining an actual start time for the floating task within the time period between the earliest start time and the latest stop time based on the earliest start time and duration of the fixed task, and arranging said floating task into the plan for the user based on the selected actual start time and the reward of the floating task.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: April 11, 2006
    Assignee: Attention Control Systems, Inc.
    Inventor: Richard J. Levinson
  • Patent number: 7025762
    Abstract: A method and apparatus to treat Barrett's tissue, a pre-cancerous condition, by removing the epithelium above the lower esophageal sphincter through cryo-ablation. An endoscope with fiber optics is used to view the operation, and a catheter for supplying liquid nitrogen is passed through the lumen of the endoscope. Liquid nitrogen at low pressure is sprayed directly onto the Barrett's tissue through the catheter while the physician views the operation through the fiberoptics of the endoscope and controls the spray via a valve. Freezing is indicated by whiteness and shows that the epithelium has been cryoablated. The apparatus can also be used to treat various other gastrointestinal tract lesions. The catheter is insulated to withstand extremely cold temperatures without becoming stiff and without affecting the inherent flexibility and maneuverability of the endoscope.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: April 11, 2006
    Assignee: CryMed Technologies, Inc.
    Inventors: Mark H. Johnston, Jennifer B. Cartledge
  • Patent number: 7025281
    Abstract: The invention is directed to programmable temperature control in which a controller may be programmed to control a thermal output of said temperature-modifying device, and to operate an air circulating system independently of the temperature-modifying device. The apparatus may incorporate a user input for entering air handling information to program the air circulating system to operate at predetermined intervals. The controller may be further programmed to receive air filtration information from the user input and to generate air filtration output information. The system may also be programmed to receive information regarding a characteristic of the air circulating system from an sensor for use in calculating the air filtration output information.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: April 11, 2006
    Assignee: Lux Products Corporation
    Inventor: Michael R. DeLuca
  • Patent number: 7026771
    Abstract: A microprocessor of the motor control apparatus acquires a zero-cross detection signal from a zero-cross detection section and a load current from a current detection section at a prescribed sampling period. The processor obtains a load current instant value every sampling period and a corresponding sine-functional value from a sine-functional value table to calculate a compensation value for the load current instant value. The processor also calculates a load current compensation total value by adding the compensation value by the predetermined number of times of sampling and compares the load current compensation total value with a load current reference value to obtain a difference therebetween. In response to the difference, an instruction value for delay time that determines the output timing of a trigger signal to a switching element is changed so that power consumption of the motor falls within a prescribed range.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: April 11, 2006
    Assignee: Toshiba Tec Kabushiki Kaisha
    Inventors: Hiroyuki Kushida, Osamu Sakurai, Akihiro Ishizawa
  • Patent number: 7026441
    Abstract: Methods and apparatus for measuring and/or controlling the temperature on the surface or inside of microchips are provided, including using thermally responsive polymers.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: April 11, 2006
    Assignee: Intel Corporation
    Inventor: Chee Choong Kooi
  • Patent number: 7025083
    Abstract: A quick closing shut-off valve includes an inlet, an outlet and a passage there between. A closing element blocks the passage when in the closed position. The closing element is interconnected to a piston via a pull rod. The piston is positioned within a working chamber that communicates with the valve outlet. A safety valve also communicates with the working chamber and is positioned above the piston. As a result, when the pressure within the tank, and thus in the working chamber, reaches a maximum permissible pressure, the safety valve opens and the pressure above the piston decreases. The piston rises as a result and pulls the closing element via the pull rod into the closed position so that the valve is closed.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: April 11, 2006
    Assignee: Chart Inc.
    Inventors: Vaclav Chrz, Gerd Kirchgassner, Petr Zaruba
  • Patent number: 7025838
    Abstract: A ferritic stainless steel sheet for use in automobile fuel tanks and fuel pipes having smooth surface and resistance to organic acid is provided. The sheet contains, by mass, not more than about 0.1% C, not more than about 1.0 Si, not more than about 1.5% Mn, not more than about 0.06% P, not more than about 0.03% S, about 11% to about 23% Cr, not more than about 2.0% Ni, about 0.5% to about 3.0% Mo, not more than about 1.0% Al, not more than about 0.04% N, at least one of not more than about 0.8% Nb and not more than about 1.0% Ti, and the balance being Fe and unavoidable impurities, satisfying the relationship: 18?Nb/(C+N)+2Ti/(C+N)?60, wherein C, N, Nb, and Ti in the relationship represent the C, N, Nb, and Ti contents by mass percent, respectively. A process for making the same is also provided.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: April 11, 2006
    Assignee: JFE Steel Corporation
    Inventors: Yoshihiro Yazawa, Osamu Furukimi, Mineo Muraki, Yoshihiro Ozaki, Kunio Fukuda, Yukihiro Baba
  • Patent number: 7026164
    Abstract: Adenovirus packaging cell lines for growth of an E1A/E1B deficient adenovirus that is substantially free of replication competent adenovirus (RCA) are provided. Methods for producing adenovirus substantially free of RCA are also provided, wherein the adenovirus is grown in a cell line containing coding sequences for adenovirus E1A and E1B, which are operably linked to promoters that lack polynucleotide sequences sharing substantial sequence identity with the native adenovirus E1A and E1B promoters.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: April 11, 2006
    Assignee: Cell Genesys, Inc.
    Inventors: Yuanhao Li, Deborah Farson, Luqun Tao, DeChao Yu