Patents Represented by Attorney, Agent or Law Firm Plotkin & Kahn PLLC
  • Patent number: 6539452
    Abstract: The present invention relates to a semiconductor memory having a pre-fetch structure. In such memory, an odd address cell array is provided with an odd address redundant cell array, and an even address cell array is provided with an even address redundant cell array, firstly, the present invention comprises a redundant memory, which stores an odd redundant address and an even redundant address, together with odd and even selection data. Since redundant memory is used flexibly on the odd side and even side, it is possible to maintain a high relief probability even when redundant memory capacity is reduced.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: March 25, 2003
    Assignee: Fujitsu Limited
    Inventor: Horoyoshi Tomita
  • Patent number: 6538288
    Abstract: An electrostatic discharge (ESD) protection structure for an integrated circuit constructed on a substrate of a first type is provided to includes a plurality of island-like distributed diffusion regions. The protection structure includes a semiconductor controlled rectifier (SCR), an MOS transistor and a plurality of island-like distributed diffusion regions of the first type. The semiconductor controlled rectifier is constructed on the base region and coupled to the integrated circuit. The SCR includes a first region of a second type formed next to the base region, a second region of the first type formed in the first region, and a third region of the second type formed in the base region. The MOS transistor has a drain coupled to the bonding pad or a VDD bus, and a gate and a source both coupled to a reference ground. The plurality of island-like distributed diffusion regions of the first type are formed in the base region and each is coupled to the reference ground.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: March 25, 2003
    Assignee: Winbond Electronics Corp.
    Inventors: Shu-Chuan Lee, Yu-Chen Lin
  • Patent number: 6536210
    Abstract: An exhaust gas purification apparatus for an internal combustion engine capable of lean operation has an Ir-containing selectively reducing catalyst and an NOx adsorptive catalyst. The Ir-containing selectively reducing catalyst in which iridium is an active species thereof and NOx is selectively reduced in a lean atmosphere by HC as a reducer is disposed in an exhaust system of the internal combustion engine. The Ir-containing selectively reducing catalyst is disposed on an upstream side of the exhaust system. The NOx adsorptive catalyst adsorbs NOx in the lean atmosphere and reduce the adsorbed NOx at a theoretical air-fuel ratio or at a rich air-fuel ratio. The NOx adsorptive catalyst is disposed on a downstream side of the exhaust system.
    Type: Grant
    Filed: July 7, 1999
    Date of Patent: March 25, 2003
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Isao Komoriya, Ken Ogawa, Yasunori Ehara, Masanori Hayashi
  • Patent number: 6538066
    Abstract: A thermoplastic elastomer composition dynamically vulcanized to a gelation rate of 50 to 95% which is superior in heat resistance and durability while maintaining flexibility and superior in air permeation preventive property which can be efficiently used as, for example, a pneumatic tire as an air permeation preventive layer.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: March 25, 2003
    Assignee: The Yokohama Rubber Co., Ltd.
    Inventors: Jiro Watanabe, Kazuto Yamakawa, Daisuke Kanenari, Noriaki Kuroda, Gou Kawaguchi, Yuichi Hara, Tetsuji Kawazura, Shigeru Yamauchi, Hideo Nemoto
  • Patent number: 6538493
    Abstract: A first transistor is turned on during operation of a circuit block, to connect a substrate of the transistor to a first substrate voltage line. A second transistor is turned on during non-operation of the circuit block, to connect the substrate of the transistor to a second substrate voltage line. ON resistance of the second transistor is higher than that of the first transistor. A source-to-substrate voltage of the transistor being not in operation is set to be higher than that of the transistor being in operation. When a semiconductor integrated circuit switches from the operation state to the non-operation state, its substrate voltage changes gradually to a second substrate voltage. Charging/discharging currents of the substrate voltage can be dispersed so that it is possible to suppress current consumption in shifting from the operation state to the non-operation state and reduce a standby current in the non-operation state.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: March 25, 2003
    Assignee: Fujitsu Limited
    Inventors: Toru Koga, Shinichi Yamada, Masato Takita
  • Patent number: 6538161
    Abstract: The objective of this invention is to provide fluorescent compounds comprising a naphthalene skeleton, an electron donating group substituted at the 2- or 1-position of the naphthalene skeleton, and an electron attractive group substituted at the 6- or 4-position of the skeleton. The fluorescent compound of this invention is capable of emitting visible light having a desired color by choosing an appropriate combination of the electron donating group A, which has an electron-pushing function, and the electron attractive group B, which has an electron-pulling function.
    Type: Grant
    Filed: January 10, 2002
    Date of Patent: March 25, 2003
    Assignee: Taiho Industries Co., Ltd.
    Inventors: Tadao Nakaya, Takao Yamauchi, Akio Tajima, Hidemasa Mouri
  • Patent number: 6538834
    Abstract: A servo controller for correcting a read position of a head when reading data recorded on a recording medium. In accordance with the amplitude ratio of data signals read from each segment of a servo section defined on a recording medium, the servo controller generates an AGC signal corresponding to the next segment before reading the next segment. The data signal read from a phase detection segment of the servo section is amplified to an amplitude greater than the predetermined determination range. The amplified data signal is converted to a two-value digital signal in accordance with the determination range. The phase used during servo control is calculated in accordance with the digital signal.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: March 25, 2003
    Assignee: Fujitsu Limited
    Inventor: Shigetaka Asano
  • Patent number: 6533389
    Abstract: The present invention relates to an ink jet printer in which drops of ink are jetted out onto a surface of a recording medium so as to record an image. The present invention is to obtain an economical ink jet printer in which a reaction force generated in the reciprocal motion of the ink jet head is simply canceled, and the ink jet printer is small and light, and less vibration is caused in the printer, and further it is possible to drive the printer with a small amount of drive energy.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: March 18, 2003
    Assignee: Fujitsu Limited
    Inventors: Masao Hiyane, Toshio Fukushima, Kazuki Ogawa, Yasuo Numata, Yuji Yoshida
  • Patent number: 6535410
    Abstract: A content addressable memory device includes a first match line which is a first one of two portions into which a whole match line corresponding to a single item of entry data is divided, and changes from a first potential to a second potential when corresponding entry data does not match an entry key, a second match line which is a second one of the two portions into which the whole match line corresponding to the single item of entry data is divided, and changes from a second potential to a first potential when corresponding entry data does not match an entry key, a first precharge circuit which precharges the first match line to the first potential, a second precharge circuit which precharges the second match line to the second potential, and a short-circuiting circuit which short-circuits the first match line and the second match line with each other prior to precharging by the first and second precharge circuits if both of the first and second match lines indicate a mismatch.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: March 18, 2003
    Assignee: Fujitsu Limited
    Inventor: Miki Yanagawa
  • Patent number: 6535965
    Abstract: A semiconductor memory device has a burst write mode in which predetermined plural command signals are input through a plurality of command pads and a mask control operation in the burst write mode is performed in response to the command signals. Therefore, the mask control in burst write mode is increased in speed to give an improved data transfer rate.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: March 18, 2003
    Assignee: Fujitsu Limited
    Inventors: Hitoshi Ikeda, Yasuharu Sato, Takaaki Suzuki, Toshiya Uchida, Kotoku Sato
  • Patent number: 6535106
    Abstract: A chip resistor reveals a crack for permitting easy detection of it in the inspection process, suffers from minimum variation of the resistance during calcination of a protection film, and is not prone to defects such as pinholes that do not come to the surface. This chip resistor is produced by forming a resistive layer on the surface of an insulating substrate, providing electrodes at both ends of the resistive layer, forming a resistive-layer protection film on the surface of the resistive layer, forming an intermediate protection film on the surface of the resistive-layer protection film, and forming a surface protection film on the surface of the intermediate protection film. In addition, in this chip resistor, the resistive-layer protection film, intermediate protection film, and surface protection film are all made of an identical material.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: March 18, 2003
    Assignee: Rohm Co., Ltd.
    Inventor: Toshihiro Teramae
  • Patent number: 6535608
    Abstract: A stereo broadcasting receiving device comprises pseudo stereo signal generation means for generating a pseudo left stereo signal and a pseudo right stereo signal from an L+R signal, first multiplication means for multiplying the pseudo left stereo signal by a first coefficient, second multiplication means for multiplying the pseudo right stereo signal by the first coefficient, third multiplication means for multiplying the L+R signal by a second coefficient, fourth multiplication means for multiplying an L−R signal by a third coefficient, coefficient determination means for determining the first coefficient, the second coefficient, and the third coefficient on the basis of the result of judgment in receiving state judgment means, means for generating a left stereo output signal on the basis of an output signal of the first multiplication means, an output signal of the third multiplication means, and an output signal of the fourth multiplication means, and means for generating a right stereo o
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: March 18, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Masaaki Taira
  • Patent number: 6535442
    Abstract: A command storing control circuit stores in storing units a plurality of commands supplied the latest of the supplied commands so as to execute the memory operation. A command reading control circuit reads the commands stored in a command storing area during a test mode. If incorrect data are written into a semiconductor memory, causing the system mounting the semiconductor memory to become inoperable, the cause of the trouble can be efficiently determined by utilizing the commands stored in the command storing area. As a result, the efficiency of development of the system can be improved, for example, and the cost of developing the system can be reduced. Moreover, the quality of the system can be also improved.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: March 18, 2003
    Assignee: Fujitsu Limited
    Inventor: Shinsuke Kumakura
  • Patent number: 6534520
    Abstract: The present invention relates to heterocyclic Compounds having antiviral activity. In particular, Compounds of formula (I): wherein B, W, X, Y, Q, R1, R2, R3, R4 and n are as defined herein, are useful in the therapy and prophylaxis of viral infection in mammals.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: March 18, 2003
    Assignee: BioChem Pharma Inc.
    Inventors: Jean Bédard, Robert Rando, Jean-Francois Lavallée, Guy Falardeau
  • Patent number: 6534914
    Abstract: An additional dielectric layer (11A) is formed on a backside of a dielectric layer (11) to protrude to the inside of a discharge space (S) and extend along an edge of a discharge cell C in parallel to the row direction. Row electrodes (X, Y) respectively have bus electrodes (Xb, Yb) extending along the edge of the discharge cells (C) in the row direction, and transparent electrodes (Xa, Ya) paired with each other in each discharge cell C. An overlap portion (m) of a proximal end (Xa3, Ya3) of each transparent electrode (Xa, Ya) connected to the bus electrode (Xb, Yb), which overlaps the additional dielectric layer (11A), is designed to be smaller in width than that of a linking portion (Xa2, Ya2) between the overlapping portion (m) and a distal end of the transparent electrode.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: March 18, 2003
    Assignee: Pioneer Corporation
    Inventors: Kimio Amemiya, Yasuhiro Torisaki
  • Patent number: 6535452
    Abstract: A semiconductor memory device includes a plurality of memory blocks, each of which is refreshed independently of one another, m (m>1) data pins, each of which continuously receives or outputs n (n>1) data pieces, a conversion circuit which converts data of each of the data pins between parallel data and serial data, m×n data bus lines on which the n data pieces are expanded in parallel with respect to each of the m data pins, m address selection lines which are connected to m respective blocks of the memory blocks corresponding to the m respective data pins, and are simultaneously activated, the activation of any one of the address selection lines connecting the data bus lines to a corresponding one of the m respective blocks and resulting in the n data pieces being input/output to/from the corresponding one of the m respective blocks.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: March 18, 2003
    Assignee: Fujitsu Limited
    Inventors: Masaki Okuda, Toshiya Uchida
  • Patent number: 6535039
    Abstract: An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD<VS.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: March 18, 2003
    Assignee: Fujitsu Limited
    Inventors: Hiromi Nanba, Tohru Mizutani, Makoto Ikeshita, Masato Takeyabu
  • Patent number: 6535950
    Abstract: A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: March 18, 2003
    Assignee: Fujitsu Limited
    Inventors: Akihiro Funyu, Shinya Fujioka, Hitoshi Ikeda, Takaaki Suzuki, Masao Taguchi, Kimiaki Satoh, Kotoku Sato, Yasurou Matsuzaki
  • Patent number: D472194
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: March 25, 2003
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Junji Tanabe, Hiroaki Nakamura, Hideyuki Ikeda, Kazumasa Takikawa
  • Patent number: D472195
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: March 25, 2003
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Toshiyuki Okumoto, Hirotsugu Nogami, Hideyuki Ikeda, Yasuo Imagawa