Abstract: A semiconductor device is built by combining together a plurality of semiconductor chips, but nevertheless allows easy functional checking of the individual semiconductor chips before they are assembled together without provision of extra pads for such checking.

Abstract: Sn—Zn alloy is plated on at least one of a first metallic member and a second metallic member, Sn—Ag alloy is used as a solder, the first metallic member and the second metallic member are connected by the solder, and a connection structure of metallic members is therefore produced. Heat degradation of plating and the contact corrosion between solder and plating can thereby be prevented, solderability can be improved, and qualities such as corrosion resistance and connecting strength at the connection structure can be improved.

Abstract: In a plasma display panel, a floating electrode (F1) is provided each portion on at least one of the front glass substrate (10) and the back glass substrate (13) facing the vertical wall (15a) of the partition wall (15) defining partition between the discharge cells (C) adjacent to each other in the row direction, and formed with the same materials as the transparent electrode (Xa, Ya) or the bus electrode (Xb, Yb).

Abstract: A vehicle clutch engagement condition determining apparatus determines the engagement condition of a clutch for disengaging an engine from a transmission. This determining apparatus estimates a motor speed corresponding value through an ECU, sets the motor speed corresponding value to the target speed of an electric motor when a gear shift lever of the transmission is operated, determines a control current value for controlling the speed of the electric motor so that the speed of the electric motor detected matches the target speed while drive wheels are driven by the electric motor and determines the engagement condition of the clutch based on an electric current deviation.

Abstract: The present invention provides a non-volatile semiconductor memory device that can protect each block without increasing a memory element area, and make an access to the memory cells in hidden blocks in a hidden mode in which the hidden blocks are accessed. This electrically rewritable non-volatile semiconductor memory device includes K non-volatile memory elements that store protection information, a non-volatile memory element that stores a protection status, and a storage area that is logically divided into 2K or less blocks. In accordance with information stored in the K non-volatile memory elements and the non-volatile memory element that stored the protection status, a write operation is inhibited in the successive bocks in storage area.

Abstract: A multiplier circuit has an encoder and a partial product bit generating circuit. The encoder receives a multiplier bit signal arid is used to output a plurality of encode signals. The partial product bit generating circuit receives the encode signals along with a multiplicand bit signal from each digit place and is used to generate a partial product bit for each digit place. The partial product bit generating circuit has a first selection circuit which is used to select a logically true signal from among the encode signals in accordance with a value of the multiplicand bit signal. Therefore, the circuit can be reduced in size by reducing the number of necessary elements without sacrificing its high speed capability.

Abstract: Spline teeth 66 formed in the inner periphery of a sleeve 45 slidably supported on a hub 63 fixed to a rotation shaft each comprise a projecting portion 66a constituted by a first inclined surface &agr;, a flat surface &ggr; and a second inclined surface &bgr;, and these projecting portions 66a bias a blocking ring via a synchro-spring 71 in an axial direction to thereby generte a synchronizing load between the sleeve 45 and a gear 37. Immediately before the projecting portions 66a of the spline teeth 66 of the sleeve 45 moving rightward mesh with dog teeth 37a of the gear 37, the second inclined surfaces &bgr; of the projecting portions 66a move and ride on the synchro-spring 71 so as to gradually reduce a pressing force axially applied to the blocking ring 67, thereby making it possible to provide a smooth mesh engagement between the spline teeth 66 of the sleeve 45 and the dog teeth 37a of the gear 37.

Abstract: A nonvolatile semiconductor memory device includes a virtual-ground memory array which includes a plurality of nonvolatile memory cells and sub-bit lines connected to the nonvolatile memory cells, first and second selection lines, first and second selection transistors which become conductive in response to activation of the first selection line, a third selection transistor which become conductive in response to activation of the second selection line, a first main bit line which is coupled to and supplies a drain potential to a sub-bit line situated on a drain side of a selected memory cell through the first selection transistor, a second main bit line which is coupled to and supplies a source potential to a sub-bit line situated on a source side of the selected memory cell through one of the second selection transistor and the third selection transistor, and a third main bit line which is coupled to a sub-bit line adjacent to the sub-bit line situated on the drain side of the selected memory cell through a

Abstract: A fuel reforming apparatus is provided for generating a hydrogen-rich gas. The fuel reforming apparatus includes an evaporator comprising an evaporation chamber for evaporating the fuel vapor by evaporating a hydrocarbon fuel-water mixture by an evaporator using a combustion gas formed in a combustor; a heating chamber for heating the fuel vapor by a combustion gas output from the evaporation chamber; and a guiding path for guiding the combustion gas output from the evaporation chamber to the heating chamber along the floor of the evaporating room. In the heating chamber, the fuel vapor generated in the evaporation chamber is uniformly heated in an atmosphere with a homogeneous temperature of the combustion gas output from a heating medium tube, while the fuel vapor is circulating in the vapor tube.

Abstract: An internal voltage generation circuit with a small area, which has many correction points and can provide an output voltage with a high precision, has been disclosed. In this internal voltage generation circuit, some resistors, among the resistors which are connected in series constituting the feedback circuit, have different resistance and transfer gates are provided in parallel to the resistors of different resistance. This configuration has a decode function and, therefore, the decoder can be eliminated and the number of sets of an inverter, a transfer gate, and a resistor can also be reduced, resulting in a reduction in area without a reduction in the number of the correction points.

Abstract: The semiconductor integrated circuit according to the present invention comprises a plurality of receiving circuits each for receiving a plurality of input signals in synchronization with a timing signal. The input signals supplied to each of the receiving circuits are made equal in propagation delay times from their respective input terminals to the receiving circuit. Since the receiving circuits can receive the input signals of little skew, the timing margin required for the reception is minimized. That is, high speed operation becomes possible. At the same time, because the input signals corresponding to each individual receiving circuit are made equal in propagation delay time, the wiring for transmitting the input signals can be arranged in a minimum area. This can reduce the chip area, with reduction in chip costs.

Abstract: A system for controlling an automatic transmission of a vehicle, in which a pressure supply time to complete removal of the clutch-stroke play is determined based on the input shaft rotational speed. And a residual oil amount in the clutch is estimated and the time is corrected by the residual oil amount. The preparatory pressure to be supplied within the time is also determined based on the input shaft rotational speed and the ATF temperature. With this, it becomes possible to effect the clutch-stroke play removal within a less variant time and with a good response, thereby decreasing the shift shock effectively so as to improve the feeling of the vehicle occupant.

Abstract: A substrate such as a sapphire substrate or the like is set to a molecular beam epitaxy (MBE) apparatus. Next, the temperature of the substrate is elevated to the temperature which is lower than the temperature at which a predetermined ZnO based oxide semiconductor layer (i.e. function layer) is grown (S1). Then, raw materials containing oxygen radical is irradiated to the substrate to grow a buffer layer made of ZnO based oxide semiconductor (S2). Subsequently, the irradiation of oxygen radical is stopped so as to eliminate the influence of oxygen onto the buffer layer (S3). Then, the temperature of the substrate is elevated to the temperature at which the predetermined ZnO based oxide semiconductor layer is grown (S4). After that, raw materials containing oxygen radical is irradiated so as to sequentially grow a ZnO based oxide semiconductor layer as a function layer (S5).

Abstract: The present invention provides a semiconductor memory device that performs a highly reliable data read operation at a high speed. This semiconductor memory device reads data stored in memory cells in accordance with a result of a comparison between a signal read out from the memory cells, which are connected to a word line, with a signal read out from a reference cell connected to a reference word line. This semiconductor memory device includes a load capacity adjustment circuit that adjusts the timing of starting up the gate of the reference cell in accordance with each location of the connection of the memory cells to the word line.

Abstract: A semiconductor memory device includes bit lines which transfer data of memory cells, a sense amplifier which is connected to the bit lines, and amplifies data on the bit lines that appears in response to an external access, and a latch circuit which is connected to the bit lines, and amplifies and latches data on the bit lines that appears as data to be refreshed.

Abstract: A semiconductor memory device includes a DQ-quantity-selection signal generation circuit which generates a DQ-quantity-selection signal indicative of a number of input/output data bits, bit lines which transfer read data and write data for memory cells, and a plurality of sense amplifiers which are connected to the bit lines, and are activated as many as indicated by the DQ-quantity-selection signal.

Abstract: An electronic circuit for measuring the position of a spatially periodic intensity pattern of incident radiation includes an array of detectors (1); two or more correlator units (2, 3) each having arrays of capacitors (12, 13) connected to a buffer (14); and a phase angle computing unit (4). The pitch of the array of detectors (1) is smaller than the pitch of the incident intensity pattern so that the latter is oversampled, yielding high accuracy. The detector outputs (17) are weighted by respective fixed capacitance values (15, 16) which vary periodically along arrays of capacitors (12, 13), and a weighted sum of outputs for each correlator unit (2, 3) is output at its respective buffer (14). The capacitance values (15, 16) of respective correlator units (2, 3) are mutually offset by a predetermined phase shift. The analog computation using capacitor arrays (12, 13) is fast and energy efficient, and can be implemented as a VLSI circuit.

Abstract: The object of this invention is to provide an illuminant, which can easily be produced at low cost. This invention is a carbazole derivative luminescent compound having a carbazole ring skeleton, to the nitrogen atom of which is attached an electron-donating group, and to the carbon atom of which is attached an electron-attracting group at the third position to the nitrogen atom.

Abstract: A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.