Patents Represented by Law Firm Poms, Smith, Lande & Rose
  • Patent number: 5648290
    Abstract: A CMOS-technology, DRAM integrated circuit includes paired P-type and N-type wells in a substrate, which wells are fabricated using a self-aligning methodology. Similarly, FET's of the DRAM circuit are fabricated in the wells of the substrate using a self-aligning methodology to provide FET's of opposite polarity in a DRAM which may have paired memory cells and dummy cells for symmetry of circuitry. The DRAM includes a multitude of annular multi-plate capacitor structures formed atop the FET's of the substrate, and plural layers of insulative dielectric with embedded bit and word traces providing for connection of the multitude of memory cells of the DRAM to external circuitry.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: July 15, 1997
    Assignee: LSI Logic Corporation
    Inventor: Abraham Yee
  • Patent number: 5646675
    Abstract: Unique digital codes are encoded on a video signal, the codes are retrieved at receivers and precise information concerning the time of occurrence, length, nature and quality of a monitored broadcast at a frame by frame level, is generated. The codes are inserted on scan lines of the video, and vary either on a field-to-field or fame-to-frame basis. The code has a repeating first part having a unique program material identifier indicating the time, date and place of encoding, and has a second portion that varies in a predetermined non-repeating sequence which varies along the entire length of the tape, thereby uniquely identifying each frame of the video program material. Also encoded upon successive frames is a cyclic counter code with a count corresponding to the sequence of the identifier data on successive frames.
    Type: Grant
    Filed: June 6, 1994
    Date of Patent: July 8, 1997
    Assignee: Airtrax
    Inventors: Robert C. Copriviza, Arnold M. Dubin, Edward B. Ackerman, Jackson B. Wood, Jeffrey S. Eakins, David D. Harmon
  • Patent number: 5642954
    Abstract: A space-saving ring binder is in a collapsed position when not in use, for example, during packing, shipping, storage, occupying shelf space, and in an upright position when in use retaining paper. The thickness of the ring binder is significantly less when in the collapsed position than when in the upright position. The ring binder includes a cover portion and a binding portion attached to the cover portion. The binding portion has a plurality of rings rotatably attached to a toggling assembly. The rings are pivotal from a collapsed position in which the rings define an acute angle with the toggling assembly to an upright position in which the rings are substantially perpendicular with the toggling assembly. The rings may be permanently locked in the upright position.
    Type: Grant
    Filed: May 15, 1996
    Date of Patent: July 1, 1997
    Assignee: Avery Dennison Corporation
    Inventor: Sydney Hudspith
  • Patent number: 5640730
    Abstract: An adjustable articulated bed having a back support section, a head rest section, an angled lifting lever, and a crank assembly operatively connecting the bed motor to the lifting lever. A slidable pin-and-slot arrangement connects the head end of the lever to the head rest section. As the lever is pivoted it first tilts the head rest section up relative to the (horizontal) back support section to a relative tilt position. Continued pivoting of the lever causes it to engage, lift and pivot the back support section up about the lifting-lever pivot axis. The head rest section, while maintaining the relative tilt position, is pivoted up with it. A polyfoam foundation affixed to the tops of both the back support and head rest sections tends to drag or lift the back support section up as the head rest section is pivoted up.
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: June 24, 1997
    Assignee: Maxwell Products, Inc.
    Inventor: Robert G. Godette
  • Patent number: 5640399
    Abstract: A single chip router for a multiplex communication network comprises a packet memory for storing data packets, a Reduced Instruction Set Computer (RISC) processor for converting the packets between a Local Area Network (LAN) protocol and a Wide Area Network (WAN) protocol, a LAN interface and a WAN interface. A Direct Memory Access (DMA) controller transfers packets transferring packets between the packet memory and the LAN and WAN interfaces. A packet attribute memory stores attributes of the data packets, and an attribute processor performs a non-linear hashing algorithm on an address of a packet being processed for accessing a corresponding attribute of said packet in the packet attribute memory. An address window filter identifies the address of a packet being processed by examining only a predetermined portion of said address, and can comprise a dynamic window filter or a static window filter.
    Type: Grant
    Filed: September 18, 1995
    Date of Patent: June 17, 1997
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, D. Tony Stelliga
  • Patent number: 5639519
    Abstract: An apparatus for producing a plasma suitable for semiconductor processing at pressures in the low millitorr range. The apparatus includes a vacuum chamber with a dielectric window, a generally planar coil disposed adjacent the window outside the chamber and coupled to an appropriate power source, and a plasma initiator disposed within the chamber. Once the plasma is initiated, the planar coil sustains the plasma by inductive power coupling. In one embodiment the plasma initiator is a secondary electrode disposed within the chamber and coupled to a second RF power source. In an alternative embodiment both the secondary electrode and a target pedestal are coupled to the secondary RF power source through a power splitter. In an alternative embodiment, the plasma initiator is used to ionize a portion of the process gas and provide a plasma that may then inductively couple with the planar coil.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: June 17, 1997
    Assignee: LSI Logic Corporation
    Inventors: Roger Patrick, Philippe Schoenborn, Mark Franklin, Frank Bose
  • Patent number: 5638293
    Abstract: A cell placement is generated for a microelectronic circuit chip. Interconnect points for cell nets are calculated, for example, as gravity points of the cells of the respective nets. Optimal positions for external connection terminals or pads along the border of the circuit are calculated as being the closest positions to the respective interconnect points. The total wirelength of the placement is calculated as including the distances between the interconnect points and the respective pads. Where initial location of the pads results in overlap thereof, clusters of pads are identified and expanded to remove the overlap. Concatenated overlapping clusters resulting from expansion are treated as new clusters and subsequently expanded until all overlap is eliminated. The centers of gravity of the clusters are preserved. During the overlap removal process, initial rectangular coordinates of the pad positions are converted into linear coordinates along the border.
    Type: Grant
    Filed: September 13, 1994
    Date of Patent: June 10, 1997
    Assignee: LSI Logic Corporation
    Inventors: Ranko Scepanovic, Patrik D'Haeseleer
  • Patent number: 5637563
    Abstract: A method for making and identifying mistletoe extracts as being of a pharmaceutical grade which is useful in treating AIDS, cancers and other diseases where the immune system is suppressed. The method is based on the discovery of five marker proteins which selectively bind with different sugars. Pharmaceutical grade extracts in accordance with the invention require certain concentration levels of each protein. An additional further requirement is that each protein fraction must meet specific bioactivity levels with respect to preventing malignant cell proliferation. Fingerprint markers with respect to viscotoxins and alkaloids present in the extract are also provided. Methods of treatment using the pharmaceutical grade mistletoe are disclosed.
    Type: Grant
    Filed: April 14, 1995
    Date of Patent: June 10, 1997
    Assignee: University of Southern California
    Inventor: Tasneem A. Khwaja
  • Patent number: 5632436
    Abstract: A photomultiplier tube, image intensifier tube, or night vision device includes a cascade of plural microchannel plates which are physically and electrically connected together to provide an electron multiplication through the microchannel plate cascade. At least two adjacent microchannel plates in the cascade are also physically interbonded to one another. The bonding of the adjacent microchannel plates may be accomplished by use of a metallic interbonding layer covering all except a peripheral edge portion of at least one face of one or both of the bonded microchannel plates, which interbonding layer confronts and bonds with the other of the bonded microchannel plates. The interbonding layer may cover only a peripheral annular portion of the one face of the one bonded microchannel plate, or only sub-areas of this peripheral annular portion of this one microchannel plate. During manufacturing of such an image intensifier tube, the microchannel plates are initially fabricated and handled as individuals.
    Type: Grant
    Filed: October 31, 1995
    Date of Patent: May 27, 1997
    Assignee: Litton Systems
    Inventor: Andreas Niewold
  • Patent number: 5631581
    Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a triangle, and includes an active area formed within the periphery. First and second terminals are formed in the active area adjacent to two vertices of the triangle respectively, and first to third gates are formed between the first and second terminals. The gates have contacts formed outside the active area adjacent to a side of the triangle between the two vertices. The power supply connections to the first and second terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor are selected for each device to provide a desired AND, NAND, OR or NOR function. A third terminal can be formed between two of the gates and used as an output terminal to provide an AND/OR logic function. The devices are interconnected using three direction routing based on hexagonal geometry.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: May 20, 1997
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben, Ashok K. Kapoor, Valeriy B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin, Alexander S. Podkolzin
  • Patent number: 5629224
    Abstract: Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.
    Type: Grant
    Filed: December 12, 1994
    Date of Patent: May 13, 1997
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch
  • Patent number: 5628403
    Abstract: A universal airplane jet engine turbine blade packing case assembly for securely holding a matched turbine blade pair of various shapes, sizes, and profiles for safe shipping and storage includes a molded housing having a base and a hinged lid, with the housing being partitioned into two sections, one section for each turbine blade. Each section includes a dial rotatably affixed to the inside of the base, with a tapered slot in the dial for slidably receiving and engaging a turbine blade root when the slot is in a vertical loading position. When the root has been slid into the dial, rotating the turbine blade causes the dial to also rotate, which causes the slot opening to rotate behind a portion of the housing such that the turbine root is now positively held within the dial. The turbine blade and dial are rotated further until the turbine blade chord is aligned vertically in a stow position.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: May 13, 1997
    Assignee: Bill Thomas Associates, Inc.
    Inventors: William A. Thomas, Jose L. Ordonez
  • Patent number: 5628413
    Abstract: A modular display stand for holding a plurality of lighting products is disclosed. The modular display stand is constructed from a plurality of modular units, each modular unit having two panels joined at a common edge to form a V-shape. The panel includes apertures for mounting the lighting products and a power strip for supplying electricity to the lighting products. The modular units are arranged so that one panel of a modular unit overlaps the panel of a second modular unit, wherein the overlapping panels are joined by a fastener. This arrangement is repeated so that the joined, complementary panels extend radially. Each modular unit can optionally be connected end-to-end or mounted against a wall, floor, or ceiling.
    Type: Grant
    Filed: September 20, 1995
    Date of Patent: May 13, 1997
    Assignee: Jimway, Inc.
    Inventors: Hong-lin Lu, Hsing-min Keng, Louis B. Kremer
  • Patent number: 5627624
    Abstract: A test reticle and alignment mark optimization method is provided for determining the optimal alignment mark size for the efficient and accurate alignment of process layers during integrated circuit manufacture. The test reticle includes a number of orthogonally arranged alignment marks of various types and sizes and one or more registration structures. The method involves the steps of determining an initial expected range of alignment mark sizes on the test reticle which are suitable for a particular application; applying the test reticle patter to test wafers; further processing the test wafers; measuring the alignment signals produced by scanning the alignment marks in the initial expected range; quantifying the alignment signal quality; and fitting the quantified alignment signal quality to a statistical model to determine a range of optimal alignment signal dimensions.
    Type: Grant
    Filed: October 31, 1994
    Date of Patent: May 6, 1997
    Assignee: LSI Logic Corporation
    Inventors: Randy Yim, Christopher Neville
  • Patent number: 5627999
    Abstract: A method of making, including a method of floorplanning, an integrated circuit includes the separation of electrical logic function cells of the integrated circuit into sets or macros of data path cells, each of which evidence a high level of similarity or repetitiveness in the integrated circuit, and into sets of random logic cells, which each are connected to data path cells but which do not meet topological and connectivity criteria for the data path cells. The data path cells are iteratively sorted according to connectivity requirements and are initially placed on a provisional floor plan of the integrated circuit in a cell-space matrix of rows and columns, the rows being of substantially uniform width to accommodate functional modules of the data path cells, and the rows being of variably height to cooperatively define the spaces of the cell-space matrix.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: May 6, 1997
    Assignee: LSI Logic Corporation
    Inventors: Eric C. Cheng, Ching-Yen Ho
  • Patent number: 5626248
    Abstract: A hand-held drinking apparatus including a vessel having an open end and a closed end, a handle associated with the vessel and extending outwardly therefrom, and an object, such as a bead, mounted for rotation on the vessel or the handle.
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: May 6, 1997
    Assignee: Talus Corporation
    Inventors: Michael McConnell, David L. McClees
  • Patent number: D380365
    Type: Grant
    Filed: March 20, 1996
    Date of Patent: July 1, 1997
    Assignee: Pacific Handy Cutter, Inc.
    Inventor: G. Gerry Schmidt
  • Patent number: D380366
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: July 1, 1997
    Assignee: Pacific Handy Cutter, Inc.
    Inventor: Gerry Schmidt
  • Patent number: D380367
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: July 1, 1997
    Assignee: Pacific Handy Cutter, Inc.
    Inventor: Gerry Schmidt
  • Patent number: D380513
    Type: Grant
    Filed: March 5, 1996
    Date of Patent: July 1, 1997
    Inventor: Hiroshi Noda