Abstract: A deep water offshore apparatus for use in oil drilling and production in which an upper buoyant hull of prismatic shape is provided with a passage longitudinally extending through the hull in which risers run down to the sea floor, the bottom of the hull being located at a selected depth dependent upon the wind, wave, and current environment at the well site, which significantly reduces the wave forces acting on the bottom of the hull, a frame structure connected to the hull bottom and extending downwardly and comprising a plurality of vertically arranged bays defined by vertically spaced horizontal water entrapment plates and providing open windows around the periphery of the frame structure, the windows providing transparency to ocean currents and to wave motion in a horizontal direction to reduce drag, the vertical space between the plates corresponding to the width of the bay window, the frame structure being below significant wave action whereby wave action thereat does not contribute to heave motion of
Abstract: A Motion Picture Experts Group (MPEG) multiplexed data bitstream includes encoded video and audio data units, which are prefixed with headers including Presentation Time Stamps (PTS) indicating desired presentation times for the respective data units. The data units are decoded, and presented at a fixed time after decoding, such that the fixed time can be subtracted from the PTS to provide a desired decoding time. The bitstream is parsed, the video and audio headers are stored in video and audio header memories, and the associated video and audio data units are stored in video and audio channel memories respectively. A first interrupt is generated each time a header is stored, and a host microcontroller responds by storing the PTS from the header and the starting address of the corresponding data unit in the channel memory as an entry in a list.
Type:
Grant
Filed:
September 9, 1994
Date of Patent:
September 24, 1996
Assignee:
LSI Logic Corporation
Inventors:
Greg Maturi, David R. Auld, Darren Neuman
Abstract: A one-piece divider assembly which is folded over along one edge may be fed into a laser printer, ink jet printer, or photocopier. The assembly includes a divider sheet having a binding edge, a reduced-thickness binding edge region extending inwardly from the binding edge, and a main body with an integral, outwardly-extending tab. The divider sheet has a folding line which is inset from and which runs parallel to the binding edge. The binding edge region has a folding portion defined on one side by the binding edge and on the opposite side by the folding line. The binding edge region also has a non-folding portion adjacent to the folding portion. The folding portion includes spaced holes for a binder. A binding edge reinforcement film may be adhered to at least a portion of the binding edge region. The folding portion of the binding edge region may be folded over at the folding line, and the folding portion may be releasably tacked with a single-use adhesive to the non-folding portion of the divider sheet.
Abstract: A photocathode which is responsive to ultraviolet light to release photoelectrons includes a supportive window layer of sapphire and a single-crystal active layer of AlGaN. Interposed between the window layer and the active layer is an interface layer which insures a low population density of crystalline defects at the interface of the interface layer with the active layer and in the active layer itself. Consequently, the photocathode is an effective emitter of photoelectrons in the transmission mode.
Type:
Grant
Filed:
July 28, 1994
Date of Patent:
September 17, 1996
Assignee:
Litton Systems, Inc.
Inventors:
Hyo-Sup Kim, John F. Krueger, Alexander L. Vinson
Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.
Type:
Grant
Filed:
June 14, 1993
Date of Patent:
September 17, 1996
Assignee:
LSI Logic Corporation
Inventors:
Michael D. Rostoker, Carlos Dangelo, Vijay Nagasamy
Abstract: A large number of possible placements of cells on an integrated circuit chip are generated and evaluated to determine the placement with the highest fitness. Cells for transposition or "swapping" within each placement using genetic algorithms are selected using greedy algorithms based on the fitness of each cell. The cell fitnesses are evaluated in terms of interconnect congestion, total net wire length or other criteria. Cells are selected for genetic crossover by sorting the cells in order of fitness and multiplying the cell fitnesses by weighting factors that increase non-linearly with rank. The cells are selected using linear random number generation such that cells with higher fitnesses have a higher probability of selection. Cells having lowest fitness are selected for mutation, and transposed to random locations, to adjacent locations, with cells having second worst fitness, to the center of mass of the respective interconnect nets, or with two or more cells in a cyclical manner.
Type:
Grant
Filed:
April 19, 1994
Date of Patent:
September 17, 1996
Assignee:
LSI Logic Corporation
Inventors:
James S. Koford, Ranko Scepanovic, Edwin R. Jones, Douglas B. Boyle, Michael D. Rostoker
Abstract: An assembly for storing and displaying discs, cassettes, game cartridges, tapes or the like, including an elongated straight side-walled storage unit forming a column of longitudinally-spaced storage slots. First and second side members are secured to the opposite lower sides of the storage unit and extend out from it. A top member is secured to the storage unit and extends up from it. The side members and top member are configured such that together with the storage unit they define in front view a readily-recognizable outline of a common (non-storage unit) object, such as a guitar or other musical instrument. The slots or rib spaces of the storage unit define, when the object is a stringed musical instrument, the frets thereof. An interesting, attractive and readily identifiable storage and display assembly is thereby defined. The side and/or top members can also provide surfaces to which holders for holding special tapes or cases are face mounted.
Abstract: A technique for hierarchical display of control and dataflow graphs allowing a user to view hierarchically filtered control and dataflow information related to a design. The technique employs information inherent in the design description and information derived from design synthesis to identify "modules" of the design and design hierarchy. The user can specify a level of detail to be displayed for any design element or group of design elements. Any CDFG (control and dataflow graph) object can be "annotated" with a visual attribute or with text to indicate information about the design elements represented by the object. For example, block size, interior color, border color, line thickness, line style, etc., can be used to convey quantitative or qualitative information about a CDFG object. Examples of information which can be used to "annotate" objects include power dissipation, propagation delay, the number of HDL statement represented, circuit area, number of logic gates, etc.
Type:
Grant
Filed:
February 10, 1994
Date of Patent:
September 10, 1996
Assignee:
LSI Logic Corporation
Inventors:
Carlos Dangelo, Daniel Watkins, Doron Mintz
Abstract: Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into, the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.
Abstract: A soft-goods type, custom "in situ" formable knee brace for supporting weakened or injured knees is disclosed having formable components which conform to the unique configuration of an individual's leg surfaces. A flexible femoral component, extending circumferentially around the anterior femur, is pivotally connected with a flexible tibial component extending circumferentially around the anterior tibia. The pivoting hinge assemblies have their axes of rotation oriented along the axis of rotation of the knee joint, and may include condylar component pads. The initially flexible femoral and tibial components are secured to the leg and held in place by adjustable straps, and may be removed or adjusted by releasing or tightening the straps. The knee brace conforms to the leg surfaces through the use of a gas and liquid permeable matrix impregnated with a water-activated urethane polymer comprising, or contained within, each component.
Abstract: A capacitive pressure sensor has a plate and a diaphragm formed of alumina and hermetically sealed in a spaced relationship, thereby defining a chamber therebetween. Conductive layers are formed on the plate and the diaphragm in opposition. An evacuation passage is formed through the plate such that the chamber pneumatically communicates with the outside. A recess is formed in an outer portion of the evacuation passage, and a tapered throat is formed in an inner portion of the evacuation passage. The chamber is substantially evacuated, and the evacuation passage is hermetically sealed by placing an indium chip and then an alumina plug in the recess. The plug is forced against the indium chip, thereby extruding indium down into the throat and up into the recess around the plug. By extruding the indium, the indium chip is plastically deformed, thereby exposing unoxidized indium to the alumina of the plate and the plug. An oxidation reduction reaction occurs and forms a chemical bond.
Abstract: A Christmas light string includes a chain including a plurality of pairs of first and second plastic links each defining at least one socket-receiving aperture. Each first link includes two protrusions each including a head shaped as an arrow head. Each second link defines two protrusion-receiving apertures. The protrusions are engageable in the plastic links. A plurality of sockets are each insertable in one of the socket-receiving apertures. A plurality of bulbs each include a husk insertable in one of the sockets.
Abstract: Method and apparatus for cooling an electronic dissipate heat. The method includes the steps of providing a heat sink made from a powdered metal, placing the heat sink in thermal communication with the electronic device and, in one preferred embodiment, circulating an ambient fluid about the heat sink. The heat sink may have a first portion configured to be in thermal communication with the electronic device and a second portion configured to dissipate heat to an ambient fluid. In one preferred embodiment the powdered metal used to form the heat sink includes copper. The powdered metal forming the heat sink may also be at least partially fused. The heat sink structure may be an integral portion of a package for an integrated circuit structure. The heat sink may alternatively be secured to the electronic device with a thermally conductive adhesive. One configuration of the heat sink may include a plurality of posts projecting from a generally flat surface.
Abstract: A semiconductor circuit package includes features forming an electrostatic charge distribution network having nodes which are defined by the electrical contact leads of the package for the semiconductor circuit, and which are effectively connected with one another by spark-gaps. In one embodiment electrical leads of the package are provided with pointed protrusions lying in the plane of the electrical leads. Accordingly, an inadvertent electrostatic discharge is distributed throughout the semiconductor circuit at safe voltage levels determined by the characteristics of the spark gaps of the charge distribution network.
Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications using a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.
Type:
Grant
Filed:
June 14, 1993
Date of Patent:
September 3, 1996
Assignee:
LSI Logic Corporation
Inventors:
Carlos Dangelo, Richard Deeley, Vijay Nagasamy, Manoucher Vafai
Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. Another aspect of the present invention provides a semiconductor device assembly including a first conductive layer with a plurality of traces formed on an insulating layer, a second conductive layer with an inner edge portion exposed within the central opening in the insulating layer, and a leadframe having a number of leads the inner end of one or more of the leads being electrically connected to an outer end of one or more of the traces.