Abstract: A barrier layer is formed over the substrate by deposition, and a first dielectric is formed over the diffusion barrier layer by deposition. A etching stop layer and a second dielectric are formed in turn over the first dielectric by deposition. Next, a hard mask is formed on the second dielectric. Then, a photoresist layer is formed over the hard mask, and defining the photoresist layer. And then dry etching is carried out by means of the photoresist layer as the mask to form a via hole. A gap-filling material is filled on the second dielectric and into the via hole by conventional partial-cured (or un-cured) spin-on glass method. A anti-reflection layer is formed over the second dielectric by deposition. Another photoresist layer is formed on the anti-reflection coating and defined the photoresist layer, and to expose the partial surface of the via hole and the anti-reflection coating.

Abstract: The present invention discloses a single poly non-volatile memory structure including a semiconductor substrate with two active areas divided by isolation regions. A control gate doped with N-type impurities is embedded in the first active area, and a first floating gate is formed thereon. A second floating gate is formed on the substrate of the second active area, and two doped regions are implanted at opposite sides of the second active areas in the substrate. A floating gate line is employed to connect the first and second floating gate for making sure that the two floating gates are in the same potential. When the control gate is biased to a voltage level, the voltage level would be coupled to the first floating gate so as to keep the second floating gate in the same potential with the first floating gate. While one of the doped regions is biased to a voltage level, electrons would eject from the other doped region and trapped in the floating gates, thereby preserving information in this memory structure.

Abstract: A method for forming semiconductor devices is disclosed. The method of the present invention includes providing a semiconductor substrate, followed by forming shallow trench isolation (STI) process, and then a dummy gate is formed by silicon nitride layer which is deposited and defined. With appropriate wet etching, this dummy poly can be removed. After local punch-through implantation, reverse offset spacer is formed to reduce Cgd (capacitance is between gate and drain) and poly-CD (critical dimension). Polysilicon is deposited followed by polysilicon CMP. After thick Ti-salicidation, the usual CMOS (Complementary Metal-Oxide-Semiconductor) processes are proceeded.

Abstract: The present invention provides a method and a device capable of manufacturing spherical semiconductor crystals continuously without contamination. A bar-shaped semiconductor material 64a is connected to a supporting member (wire 50) and descends at a preset speed. The bar-shaped semiconductor material 64a is preheated by the preheating portion 56c of a heater 56 to a predetermined temperature. Afterward, the preheated bar-shaped semiconductor material 64a further descends, and the surface of the semiconductor material melts through heating of the melting portion 56d of the heater 56 to form liquid drops 64b. The liquid drops 64b accumulate at the lower end of the bar-shaped semiconductor material 64a and drop down by their own weights. The liquid drops 64b cool down during free fall and become solid spherical semiconductor crystals 64c without deformation. An impact absorbing material 62 absorbs the impact of the falling spherical semiconductor crystals 64c and retains them.

Abstract: An electrostatic discharge (ESD) device comprising a field implant region being in the substrate. A STI is on the field implant region and a gate oxide layer is on the STI. A S/D region is below the gate oxide layer and is on the two sides of the STI. A gate is on the gate oxide layer and a spacer is on the sidewall of the gate. Some alternatives can be devised as follows: (1) The length between STI region and LDD region is zero; (2) without LDD region; (3) with an N well region below the field implant region, the LDD region and S/D region; (4) with a deep N well region below the N well region. The ESD device in the present invention has a deeper current path to increase the heat dissipation through a larger device volume. Therefore, the device can sustain a much higher ESD robustness in a smaller silicon area.

Abstract: A method for forming MOSFET is disclosed. The method includes firstly providing a substrate, on which a gate without spacer is already formed. A first spacer is formed on sidewall of the gate, a lightly doped drain is subsequently formed in the substrate. Next, a second spacer is formed on the first spacer. Finally, a heavily doped drain is formed in the substrate. The present invention can enhance stability of resistance of the gate and reduce pollution of the machine. Therefore, quality and efficiency of the fabrication of MOSFET will be enhanced.

Abstract: Polypropylene films having a base layer of a propylene polymer with at least one matte outer layer of a blend of a polyether block polyamide, polypropylene, and polybutene-1, the polybutene-1 representing from 40 to 60 wt. % of the blend. Such films have shown good antistatic properties combined with particularly low heat seal thresholds compared with similar films without the polybutene-1 in the outer layer or layers.

Abstract: The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a first pad oxide layer on a semiconductor substrate, an N-well region is defined by first implanting in the semiconductor substrate. After removing the first photoresist layer, a second ion implantation is performed to define a P-well region. Next, both the silicon nitride layer and the first pad oxide layer are removed. A high temperature long time anneal is done to form a deep twin-well. A plurality of LPD oxide trench isolation regions is formed to define an active area region. A second pad oxide layer is formed on the substrate. Finally, the standard processes can be employed for fabricating the CMOS transistors on the substrate.

Abstract: A structure for forming a laterally diffused metal-oxide semiconductor is disclosed. The structure will include the following portions. They are a semiconductor layer with a conductivity type, a field insulating region into the semiconductor layer, a gate electrode formed over at least a portion of a channel region and insulated therefrom. The first drain region without an oxide top surface is formed beside one side of the gate electrode into the semiconductor layer. A second drain region is formed in the semiconductor layer. Also, a lightly doped portion borders the channel region and the neighbouring field insulating region. The main portion neighbors the oxide top surface and is spaced from the channel region by the lightly doped portion. The main portion has a second doping concentration that is less than the first doping concentration. The deep portion has a third doping concentration that is less than the second doping concentration.

Abstract: The present invention provides a method for controlling the critical dimension of a mask in dual damascene process. The method comprises providing a semiconductor structure which has a contact pattern thereon. A dielectric layer, such as a spin-on glass layer, is formed on the semiconductor structure and the contact pattern. Then a photoresist layer is formed on the dielectric layer. Next, the photoresist layer and the dielectric layer are etched to expose partial the semiconductor structure. Then the exposed semiconductor structure is removed followed by removing the total photoresist layer and the total dielectric layer.