Abstract: A method for converting a facsimile-based vertical resolution to a printer-based vertical resolution is disclosed. The printer-based vertical resolution is firstly divided by using the facsimile-based vertical resolution to obtain a quotient and a remainder both being integers. All the data lines of the printing job are repeatedly generated for “quotient” times. Next, some data lines that their total number equals to the remainder are selected from the repeatedly data lines for further generated once than the other is. The selected data lines can be randomly or fixed selected from the data lines.

Abstract: A scaled stack-gate non-volatile semiconductor memory device having atapered floating-gate structure is disclosed by the present invention, in which a stack-gate structure including a masking dielectric layer over a control-gate layer over an intergate dielectric layer over a tapered floating-gate layer on a thin tunneling-dielectric layer is formed on a semiconductor substrate having an active region isolated by field-oxides and is oxidized. A deeper double-diffused source region having a graded doping profile formed near a gate edge and a shallow drain diffusion region are formed as the first embodiment of the present invention. The deeper double-diffused source and drain regions having a graded doping profile formed near two gate edges are formed as the second embodiment of the present invention. The shallower double-diffused source and drain regions having a graded doping profile formed near two gate edges are formed as the third embodiment of the present invention.

Abstract: A method for updating a printer firmware is disclosed. The method achieves updating a printer firmware by use of downloading a printer firmware from the network or some media. More specifically, a Printer Job Language (PJL) Download Command of printer firmware is downloaded through an input port of the printer, such as serial port, parallel port or a network interface. The Printer Firmware Blocks of the printer firmware are then written into a nonvolatile memory of the printer, such as a Flash ROM to achieve in printer firmware updating.

Abstract: A stack-gate structure including a masking dielectric layer over a control-gate layer over an intergate dielectric layer over a floating-gate layer formed on a gate-dielectric layer is formed on a semiconductor substrate having an active region isolated by field-oxides and is oxidized to form a first dielectric layer over the sidewalls of the control-gate layer, a second dielectric layer over the sidewalls of the floating-gate layer, and a thicker oxide layer over each side portion of the active region having a gradedoxide layer formed near two gate edges. An integrated source/drain landing island having a portion formed over a source/drain diffusion region for contact and an extended portion formed over a second dielectric layer and on a graded-oxide layer is acted as a field-emission cathode/anode. The scaled stack-gate flash memory device of the present invention can be programmed and erased through two-tunneling paths or one tunneling path without involving the channel region.

Abstract: In accordance with the present invention, a method for forming a via-first dual damascene interconnect structure by using gap-filling material whose thickness is easily controlled by a developer is provided. The essential part of the present invention is the application of gap-filling materials such as novolak, PHS, acrylate, methacrylate, and COMA to fill vias. Filling vias with these materials can get a greater planar topography for trench patterning due to its excellent gap-filling capacity, protect the bottom of vias from damage during the trench etch, and prevent the fence problem by using a developer to control its thickness in vias.

Abstract: The present invention provides a checking alignment method for a printed circuit board (PCB). The present method comprises following steps. First, a substrate and a PCB are provided. Then, a tape automated bonding process is performed to attach the substrate and the PCB by using a plurality of tapes. Next, a welding process is performed to connect original dummy lines on the substrate, those tapes, and the PCB to make a testing circuit for checking alignment. The present invention uses visible processes and equipment to check alignment. The present invention can judge more than two wrong alignment positions and quickly find each of wrong positions.

Abstract: A bonding pad structure of semiconductor device having improved bondability is disclosed. The bonding pad structure uses at least one level comprising conductive islands and conductive plugs used as fasteners to prevent the bonding pad layer from peeling and cracking during the bonding process.

Abstract: The scaled MOSFETs having a conductive barrier-metal layer sandwiched between a metal layer or a thick silicide layer on the top and a first conductive gate layer at the bottom are disclosed by the present invention, in which the first conductive gate layer is etched to form a steep-gate structure or a taper-gate structure. The metal layer is encapsulated by a second masking dielectric layer formed on the top and a first dielectric spacer formed on both sides, no interaction would occur between the metal layer and the first conductive gate layer, a highly-conductive nature of the metal layer for gate interconnection can be preserved. A thick silicide layer is formed by a two-step self-aligned silicidation process and a conductive barrier-metal layer is formed to eliminate the interaction between the thick silicide layer and the first conductive gate layer, a highly conductive nature of the thick silicide layer for gate interconnection can be obtained.

Abstract: The present invention provides a method for forming capacitor of a dynamic random access memory cell. The method comprises providing a substrate and the word line structures formed thereon. A first dielectric layer is deposited on the substrate and the word line structures. A first polysilicon layer is deposited to form bit line contacts and bit lines. A second dielectric layer is formed on the first dielectric layer and the bit lines. The partial second dielectric layer is removed to form at least a wall structure in the second dielectric layer. The partial second dielectric layer and partial first dielectric layer are removed to form a capacitor contact opening. A second polysilicon is deposited into the capacitor contact opening and on the wall structure and the second dielectric layer. The partial second polysilicon is removed to form a capacitor node whereby a side-wall of the capacitor node is adjacent to the wall structure.

Abstract: This invention relates to a method that prevents by-productions from moving from a spacer. In particular by using an offset liner, a liner with a treated surface and a spacer that is formed by using the atomic layer deposition method or the rapid thermal chemical vapor deposition method. The present invention uses a liner, whose surface is treated, and a spacer, which is formed by using the atomic layer deposition method or the rapid thermal chemical vapor deposition method. This prevents by-product ions from moving from the spacer to other regions by using actions in diffusion and drift to affect the voltage stability of the semiconductor device after the current is connected. This defect will further affect qualities of the semiconductor device.

Abstract: This invention increases the overlapped area between the diffusion area and the borderless contact by using optical proximity correction (OPC) method. The method includes performing an optical proximity correction on an outer corner of an active area mask to enlarge a portion of an outer corner of an active area on a substrate in a photolithography process, wherein the outer corner of the active area is used to make contact with a borderless contact. The enlarged portion of the outer corner of the active area increases the overlapped area between the borderless contact and the active area, and reduces borderless contact leakage.

Abstract: This invention uses the pattern-based signal to accelerate the evaluation process as a means to replace complicated computing procedures. This invention is constructed through implementing absolute coordinates to produce pattern-based signals by position and two optical sensor signals, and through conducting the feature extraction process. This process produces feature signals of sidelong and overlapped issues. Furthermore, through transforming signals, feature signals can be handled by the digital data processor. Thus, this invention can achieve the three main objectives of wafer mapping.

Abstract: A method to improve nitride floating gate charge trapping for NROM flash memory device is disclosed. The present invention uses the SiON to replace the SiN of the NROM floating gate of the prior art. This arrangement improves the endurance and the reliability of the device and also extends data retention times. The present invention also discloses the integrated processes to fabricate the NROM flash memory device. Using the processes, the steps of fabricating the NROM are efficiently reduced, and the defects caused by the cleaning steps are eliminated.

Abstract: Methods for removing a silicon-oxy-nitride layer and wafer surface cleaning are disclosed. The method for removing a silicon-oxy-nitride layer utilizes a solution of ethylene glycol and hydrogen fluoride to completely remove the silicon-oxy-nitride layer from a substrate. Moreover, the method for wafer surface cleaning also uses a solution of ethylene glycol and hydrogen fluoride to remove chemical oxide or native oxide from wafer surfaces and an ethylene glycol solvent to rinse the wafer surfaces.

Abstract: Polymeric films including a layer of propylene resin having microvoids therein, the microvoids having been formed by stretching a web containing the beta-form of polypropylene, have shown low static cling when being unwound from rolls in labelling operations and also during destacking of pre-formed labels. The invention provides labels formed from such films.

Abstract: The present invention provides a light semiconductor device comprising a substrate and a first semiconductor structure on the substrate. A light emitting structure is on a first portion of the first semiconductor structure. A first contact structure is on a second portion of the first semiconductor structure. The second portion is separated from the first portion of the first semiconductor structure. The first contact structure has a first shape. A second semiconductor structure is on the light emitting structure. A transparent contact is on the second semiconductor structure and has a cut-off portion to expose the portion of the second semiconductor structure and a second shape. A second contact structure is on the cut-off portion of the transparent contact. The second contact structure contacting the second semiconductor has a third shape.

Abstract: A method for forming self-aligned split gates in a flesh memory is disclosed. The method includes two-step lithographic definition of a split gate and nitride spacer formation of the gate. The two-step lithography procedure is designed to assist the nitride spacer formation. The nitride spacer formation is used to facilitate gate etching in a self-aligned manner so that the channel length of the split gate is under proper control and the effect of gate misalignment can be totally avoided. The product quality of the flesh memory therefore gets improved.

Abstract: The present invention relates to a device of internal probe pads used in failure analysis. The invention provides a circuitry which comprises a plurality of probe pads placed in the last metal layer of a die. Each probe pad is divided into several conductive regions, and each conductive region is selectively connected to one of the contacts of the internal circuitry within the die by interconnects. The circuitry within the die is placed into a mode by supplying signals to parts of the plurality of probe pads, wherein at least one probe pad is used to transmit the signals into the circuitry and another one of the probe pads is grounded.

Abstract: A method of fabricating a memory device and a logic device on the same chip is described, wherein the memory device has a first gate on a first region of the chip, and wherein the logic device has a second gate with a sidewall on a second region of the chip. A conductive layer and a first suicide layer are sequentially formed over the first and the second regions of the chip. Over the first region of the chip, the first silicide layer and the conductive layer are patterned to form the first gate. Ions are first implanted into the first region of the chip, by using the first gate as a mask, to form a first doped region. A dielectric layer is formed to cap the first gate, the first doped region and the first region of the chip. The first silicide layer over the second region of the chip is removed. Over the second region of the chip, the conductive layer is patterned to form the second gate.

Abstract: The proposed method of the present invention forms MOSFETs with improved short channel effects and operating speeds over conventional devices. The method for fabricating MOSFETs includes the following steps. At first, isolation regions are formed on a semiconductor substrate and a gate insulating layer is formed on the substrate. A first conductive layer is then formed on the gate insulating layer and a first dielectric layer is formed on the first conductive layer. A removing process is performed to remove portions of the gate insulating layer, the first conductive layer and the first dielectric layer to define a gate structure. A layer formation step is carried out to form a thermal oxide layer on the substrate and on sidewalls the first conductive layer. Doped dielectric sidewall spacers are then formed on sidewalls of the gate structure. A removing step is carried out to remove portions of the thermal oxide layer uncovered by the doped dieletric sidewall spacers.