Abstract: The invention relates to a process for the preparation of molecularly imprinted polymers useful for separation of enzymes, which comprises the steps of reacting a complex of enzyme and affinity monomer, a comonomer and a crosslinker, with a polymerization initiator and a polymerization accelerator at ambient temperature and pressure for a period ranging between 2 to 24 hrs, thereby obtaining a crosslinked polymer, crushing the cross linked polymer obtained to fine particles, adding a solvent and extracting imprinted enzyme from the polymer, obtaining the molecularly imprinted polymer, contacting the imprinted polymer with aqueous solution containing imprinted enzyme or a mixture of imprinted enzyme and other enzymes and isolating the enzyme-adsorbed polymer.

Abstract: A method of removing the micro-scratches on a metal layer is described, wherein the metal layer is formed on a barrier layer conformally onto a dielectric layer having a hole thereon, and wherein the metal layer over-fills the hole. The method comprises three chemical-mechanical polishing steps as described hereinbelow. The first chemical-mechanical polishing step is that oxidizing and polishing away the metal layer outside the hole, with a first slurry, wherein the first slurry has a chemical solution and has a plurality of abrasive particles. The second chemical-mechanical polishing step is that polishing away the barrier layer outside the hole, with a second slurry, whereby a plurality of micro-scratches are formed on the metal layer after the barrier layer is chemical-mechanically polished. The third chemical-mechanical polishing step is that buffing the metal layer, with the first slurry, thereby removing the micro-scratches on the metal layer.

Abstract: An automatic method detects missing lines occurred in an image, thereby identifying possible internal problems in the scanner. The method comprises the following steps. First, from the image of a slanting line, the pixel having gray levels closest to the median value of the predetermined highest gray levels and set a fault tolerance value are identified. Then the pixel as (Xi,Yj). Then, the gray levels of the pixels on (Xi,Yj) and (Xi−1,Yj+1) are compared. If the gray-level difference between these two pixels is larger than the fault tolerance value, the occurrence of a missing line is determined. To determine the total number of missing lines on that row, the gray levels to check if (Xi−2,Yj+1)≦(Xi,Yj)<(Xi−1,Yj+1) are compared. If not, the shift index k is incremented by one repeatedly until the gray-level difference is correspondent to the predetermined comparison condition.

Abstract: A four-transistors SRAM cell, which could be viewed as at least including two word line terminals, comprises following elements: first word line terminal, second word line terminal, first bit line terminal, second bit line terminal, first transistor, second transistor, third transistor, and fourth transistor. Whereby, gate of first transistor is coupled to first word line terminal and source of first transistor is coupled to the first bit line terminal, gate of second transistor is coupled to second word line terminal and source of second transistor is coupled to second bit line terminal, source of third transistor is coupled to drain of first transistor and gate of third transistor is coupled to drain of second transistor, source of fourth transistor is coupled to drain of second transistor and gate of fourth transistor is coupled to drain of first transistor.

Abstract: A method for forming doped p-type gate is disclosed as the following description. The method includes that, firstly, a semiconductor substrate is provided. The semiconductor substrate is etched to form a concave portion as a shallow trench isolation. A first silicon dioxide is filled into the shallow trench isolation. A n-type well is formed into the semiconductor substrate. A silicon germanium layer, named as the doped p-type layer is formed on the surface of semiconductor substrate and the surface of shallow trench isolation. A silicon nitride layer, named as the anti-reflection layer is formed on the surface of silicon germanium layer. The portions of silicon nitride layer and the portions of silicon germanium layer are etched as a gate region. The source/drain extension is formed. A second silicon dioxide layer is deposited over the surface of semiconductor substrate and the surface of nitride layer. The second silicon dioxide layer is etched as a spacer beside the sidewall of gate region.

Abstract: The present invention is a method for forming a gate electrode of a transistor in integrated circuits, where the gate electrode is formed by a damascene process. First, a substrate is provided with a gate dielectric layer thereon and a first gate layer is formed on the gate dielectric layer. Next, a first silicon oxide layer is deposited on the first gate layer and an opening through the first silicon oxide layer is formed by an etching process. Then, a first spacer is formed on sidewalls of the first silicon oxide layer in the opening and then the opening is filled with a second gate layer. Following, the first silicon oxide layer and the first spacer are removed to form a gate structure. Next, the first gate layer and the gate dielectric layer around the gate structure are removed. Then, a lightly doped drain, a second spacer, and a source/drain region are formed sequentially in the transistor.

Abstract: An improved method for reworking photoresist is provided for decreasing cycle time of photoresist reworking process. A semiconductor substrate with an underlying layer is provided for patterning. A photoresist pattern is formed on the underlying layer. A photoresist reworking process is performed after an after-development-inspection (ADI) is performed. The photoresist reworking method comprises the following steps. The semiconductor substrate is placed in organic stripper for removing the most portion of the photoresist pattern. Subsequently, the semiconductor substrate is placed in a single-wafer processor and an UV/O3 dry ashing is then performed to remove completely the residual photoresist pattern on the underlying layer. A new photoresist layer is deposited on the underlying layer after the photoresist pattern removed completely.

Abstract: The invention disclosed herein is related to a photoresist coating system that significantly prevents performance of the system being degraded by any bubble in, liquid photoresist. The proposed system comprises a pump, a series of pipelines, a reactor, a tank, a capacitor sensor, a photochopper sensor and a controller, where the capacitor sensor is coupled to the pipeline and the photochopper sensor is coupled to the pipeline. Thus, any bubble inside the pipeline is detected by the capacitor sensor or the photochopper sensor. In other words, any bubble in the photoresist is detected. The operation of the present photoresist coating system is terminated by the controller to protect any wafer inside the reactor, and a warning alarm is activated by the controller.

Abstract: The present invention proposes a shallow trench isolation region in a semiconductor substrate for ULSI devices. The trench region includes a thermal oxide film formed on the bottom and the sidewall, a CVD dielectric film formed on the bottom of the thermal oxide film, and a channel stop region formed beneath the bottom of the thermal oxide film. The processes described as follows. Forming a pad oxide/silicon nitride layer on the substrate, the trench region and active area are defined. After silicon spacers are formed, the silicon substrate is recessed to form trench region by using the silicon nitride layer and silicon spacers as etching mask. A channel stopping implantation is performed. Then a thermal oxide film is regrown on the trench surface. After removing the silicon nitride layer, a thick CVD dielectric layer is deposited on the substrate. The dielectric film outside the trench region is removed by a CMP process, and thus the present invention complete.

Abstract: A method for fabricating a high vltage device with double diffusion structure provides a pad oxide layer on a silicon substrate. A silicon nitride layer is formed and patterned to expose isolation regions. A first mask covers the partial isolation regions spaced from the silicon nitride layer. A well region is formed underlay the silicon nitride layer. A second mask covers the partial isolation region spaced from the silicon nitride layer and the partial silicon nitride layer. First doped regions are formed underlay the partial silicon nitride layer. Then the isolation regions are formed partially on the first doped regions. Next, a third mask covers the pad oxide layer and the partial isolation regions and second doped regions are formed spaced from the first doped regions and below the isolation regions. A gate is formed and located between the first doped regions and a spacer on a side-wall thereof. Third doped regions are formed in the first doped regions.

Abstract: A rotary piston internal combustion engine comprises a substantially circular-cylindrical compression space (3) and a substantially circular-cylindrical working space (4), rotary pistons (7, 8) which can rotate together about an axis of the compression space (3) and the working space (4), being disposed in the compression space (3) and the working space (4) are slides (19) which are arranged so as to be movable in the radial direction in order to abut sealingly the surface of the respective rotary piston (7, 8). The periphery of the working space has a first exhaust aperture (26). The working space has further exhaust apertures (27) which can be closed by exhaust valves (15) which can be closed and opened successively by means of an adjusting arrangement (17).

Abstract: A SEG combined with tilt implant method for forming semiconductor device is disclosed. The method includes providing a semiconductor structure which comprises an active area in between isolation regions in a substrate with the active area having a gate electrode formed thereon, wherein a spacer is formed on the sidewall of said gate electrode. Then, selective epitaxial growth regions are formed on the active area and the gate electrode. Next, the active area is implanted with an angle to form source/drain regions beside the bottom edge of the gate electrode. Then, the salicide process and backend processes are performed.

Abstract: A method and system for simplifying required printer commands and facilitating print speed of both laser and inkjet printers is disclosed. When an operating system outputs a print page, a printer driving unit firstly estimates the time respectively consumed by applying the raster bitmap and high-level printer language approaches. Estimation of the printer driving unit is then routed into a print page processing unit for further processing. The print page is manipulated by using the raster bitmap approach in the print page processing unit when the time consumption of the print page estimated by using the raster bitmap approach is less than the other one. Otherwise, the print page is divided into a plurality of print bands for further processing. Complexity of the printer commands required for each print band is then estimated to judge whether the complexity is higher than a predetermined band threshold.

Abstract: A method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source/drain junctions is described. A gate structure having a gate insulating layer, a first conductive layer and a first dielectric layer is formed on a substrate. A thermal oxide layer is formed on the substrate and on sidewalls of the first conductive layer. Sidewall spacers are formed on sidewalls of the gate structure. The thermal oxide layer uncovered by the sidewall spacers is removed. The substrate is isotropically etched to form recessed regions on the substrate in regions uncovered by the gate structure and the sidewall spacers. A first metal layer is formed on the substrate after the first dielectric layer is removed. A source/drain/gate implantation is performed to the substrate, thereby forming source/drain regions under the recessed regions.

Abstract: A dual gate oxides' process for mixed-mode IC is provided. More particularly, the present invention relates to a dual gate oxides' process for mixed-mode IC, which protects and improves the dual gate oxides' quality.

Abstract: A method for fabricating a non-volatile memory on the semiconductor substrate is disclosed. First of all, a plurality of trench isolation regions are formed. Then, firstly implanting ions of a first conductivity type and second conductivity type are carried out. Secondly implanting ions of the first conductivity type and second conductivity type are carried out. Then, a first oxide layer is deposited and the first oxide layer is removed. A second oxide layer is deposited. A portion of second oxide is removed, thus, a portion of second oxide layer is remained. A third oxide layer is formed. A first polysilicon layer is formed. The first polysilicon layer is etched. A oxide-nitride-oxide layer is formed. Consequentially, the oxide-nitride-oxide layer are all etched. The second polysilicon on is formed. A portion of the second polysilicon layer, a portion of the first polysilicon layer, a portion of the third oxide layer and a portion of the second oxide layer are all etched. Thus, capacitor columns are formed.

Abstract: A replaceable and modularized integrated circuit's socket. The modularized socket comprises: (1) a base unit, it further consists of a base, contact pins and an elastomer. The contact pin will provide the electrical connection of the other elements, the elastomer provides the compactness of the assembly. (2) an interposer, there are positioning holes, contact pads and conducting wires in this interposer. (3) an adapter unit, the unit is capable of positioning the integrated circuit device and includes a depressor to suppress or release the integrated circuit. (4) a cover unit, the cover unit is coupled to said adapter and is capable of moving up and down vertically and drive the depressor to press or release the integrated circuit device. The modularized socket can fit the integrated circuit devices with different sizes and pin assignment, also much easier to repair.

Abstract: The present invention relates to improved chemical mechanical polishing apparatus, which reduce air sharp pressure on the polish head for preventing the breakage unpolished wafer. The improved chemical mechanical polishing apparatus of present invention is composed of a wafer head, a polish head, a damper and a sensor. The flowing speed of gas is reduced by making the diameter of the gas line connected to the damper air inlet smaller than the diameter of the gas line connected to the damper air outlet. The initial air sharp pressure is reduced and make &Dgr;P=Pwafer−Ppolish<0, by adding an air temporary storage machine in between the inlet and the outlet.

Abstract: A new method for forming integrated circuits is disclosed. The method includes the following procedures. A substrate over which a high integration region and a low integration region beside the high integration region are formed. Then dummy layer is formed on the low integration region. Next, a dielectric layer is formed on the high integration region and the dummy layer on the low integration region. Finally, the dielectric layer is planarized.

Abstract: A sleeve means is described. The sleeve means comprises a round plane and ring-shaped side adjacent to the round plane. The round plane has a central hole and six periphery holes thereon. The central hole and six peripheral holes respectively correspond to a central opening and six screw holes of a heater adapter flange used in Gasonics L3510 (trademark) etcher. The sleeve means could be jacketed onto the heater adapter flange for dispersing the stress on and reducing deformation of the heater adapter flange when the heater adapter flange is mounted on the chamber of the etcher.