Patents Represented by Attorney R. J. Meetin
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Patent number: 4739191Abstract: An on-chip regulated substrate bias voltage generator for an MOS integrated circuit includes a ring oscillator (10) for developing a true signal and its complement. The signals are applied to a charge pump (12) that includes two capacitors (C1 and C2) and a plurality of rectifiers (22, 24, and 26). The charge pump produces a substrate bias voltage (V.sub.BB) which is supplied to the gate of a depletion-mode field-effect transistor (28) whose source receives a reference voltage (V.sub.SS). The transistor forms part of a control circuit (14) coupled to the ring oscillator. In the N-channel case, the charge pumping action on the substrate drives the substrate bias negative until it reaches the sum of the reference voltage and threshold voltage of the depletion-mode transistor. This enables the control circuit to control the operation of the ring oscillator so as to regulate the substrate bias voltage.Type: GrantFiled: April 27, 1981Date of Patent: April 19, 1988Assignee: Signetics CorporationInventor: Deepraj S. Puar
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Patent number: 4736271Abstract: A protection device (14) for an integrated circuit (12) created on a semiconductor body (24 and 26) utilizes one or more semiconductor diodes (D.sub.L and/or D.sub.H) that have subsurface PN junctions (46 and/or 56) for preventing high-magnitude voltages, such as those generated by electrostatic discharge, from damaging sensitive electronic elements of a protected circuit component (16) formed from part of the body. The device is fabricated by an epitaxial layer/double buried region process.Type: GrantFiled: June 23, 1987Date of Patent: April 5, 1988Assignee: Signetics CorporationInventors: William D. Mack, Richard H. Lane
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Patent number: 4727409Abstract: A semiconductor PROM contains a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22 and 24) fully adjoining a recessed oxide insulating region (16). The PN junction (30) of the upper diode of each pair lies in non-monocrystalline semiconductor material. A composite buried layer consisting of buried regions (32) which adjoin the insulating region below the lower cell regions (20) and a buried web (44) which laterally surrounds each buried region is employed to improve programming efficiency as well as provide intermediate electrical connections.Type: GrantFiled: August 5, 1985Date of Patent: February 23, 1988Assignee: Signetics CorporationInventors: George W. Conner, Ronald L. Cline
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Patent number: 4703206Abstract: A field-programmable logic architecture is centered on a single array of programmable gates that perform either logical NAND or logical NOR operations. Foldback loops can be readily programmed through the array to enable the user to achieve different numbers of logic levels.Type: GrantFiled: November 19, 1985Date of Patent: October 27, 1987Assignee: Signetics CorporationInventor: Napoleone Cavlan
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Patent number: 4694566Abstract: A semiconductor PROM containing a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22) fully adjoining a recessed oxide insulating region (16) is fabricated by a process in which the insulating region serves as a mask to control the lateral extents of the dopants utilized to define the diodes. The intermediate cell regions are ion implanted to obtain maximum dopant concentration near their mid-points. This facilitates programming operation.Type: GrantFiled: July 19, 1985Date of Patent: September 22, 1987Assignee: Signetics CorporationInventors: George W. Conner, Raymond G. Donald, Ronald L. Cline
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Patent number: 4692991Abstract: During the deposition of a metallic layer on an N-type semiconductive region to form a Schottky diode in a structure placed in a highly evacuated chamber, at least one selected gas is introduced into the chamber to control the forward voltage across the diode.Type: GrantFiled: July 19, 1985Date of Patent: September 15, 1987Assignee: Signetics CorporationInventor: Ronald C. Flowers
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Patent number: 4678947Abstract: A circuit capable of simulating a transistor or a semiconductor diode with controllably adjusted voltage characteristics contains a main transistor (Q0). An input voltage (V.sub.CS) to a control system (8) is amplified with a gain set by a pair of resistors (R1 and R2) to produce a control voltage (V.sub.C) for the transistor. This downscales the forward voltage characteristics of the circuit from those of the transistor. A floating power supply (10) in series with the control electrode of the transistor permits upscaling or further downscaling of the circuit voltage range.Type: GrantFiled: October 5, 1984Date of Patent: July 7, 1987Assignee: Signetics CorporationInventors: Johan H. Huijsing, Timothy A. Dhuyvetter
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Patent number: 4677315Abstract: A circuit switches with a hysteresis defined by separately controllable thresholds which can be made largely independent of temperature and fabrication conditions. The circuit contains a pair of differential portions (21 and 22) and an arithmetic component (24). The hysteresis is introduced into the circuit by using positive feedback to control the position of a switch (23) in such a manner as to change the transconductance of the circuit as it is switching.Type: GrantFiled: July 28, 1986Date of Patent: June 30, 1987Assignee: Signetics CorporationInventors: Robert A. Blauschild, Edmond Toy
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Patent number: 4674090Abstract: A pair of complementary logic gates (A and B) are used to test for faults in a group of electronic components (C1-C3) which provide respective component signals (S1-S3) indicative of their condition. One (A) of the gates ideally generates the logical OR or NOR of the component signals. The other (B) ideally generates their logical AND or NAND. The test procedure involves providing the components with information patterns that would ideally cause all the component signals to go to a logical "0" in one step and to logical "1" in another step. The actual values of the gate output signals (OA and OB) during these two steps are then compared with the respective ideal values to assess the condition of the components.Type: GrantFiled: January 28, 1985Date of Patent: June 16, 1987Assignee: Signetics CorporationInventors: Kong-Chen Chen, Kees Hage
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Patent number: 4649352Abstract: An input portion (4, 6) of a differential amplifier circuit amplifies a differential input signal to produce an amplified signal between a pair of terminals. A summing section contains two complementary pairs of like-polarity amplifiers (13, 14 and 19, 20). Each has a first flow electrode, a second flow electrode, and a control electrode. A substantially constant bias voltage is supplied to the control electrodes of the first pair (13, 14) whose second electrodes are respectively coupled to the second electrodes of the second pair (19, 20). Their first electrodes are respectively coupled to the terminals and to corresponding impedance elements (11, 12). The control electrodes of the second pair are coupled together to receive a voltage dependent on the voltage at the second electrode of one (13) of the first pair so as to produce a representative output signal at the second electrode of the other (14) of the first pair.Type: GrantFiled: June 16, 1986Date of Patent: March 10, 1987Assignee: Signetics CorporationInventor: Robert A. Blauschild
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Patent number: 4641046Abstract: A NOR gate consisting of a set of input FET's (Q1.sub.1 -Q1.sub.M) has a clamp (12/ Q2) that, when at least one of the input FET's is turned on, clamps the logical low level of the gate output voltage at a value which is largely constant irrespective of how many of the input FET's are conductive.Type: GrantFiled: June 17, 1985Date of Patent: February 3, 1987Assignee: Signetics CorporationInventors: Scott T. Becker, Michael J. Bergman, Shueh-Mien Lee
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Patent number: 4631113Abstract: A portion (28) of photosensitive material is created by an underetching/shadowing technique in such a manner as to have an extremely narrow width.Type: GrantFiled: December 23, 1985Date of Patent: December 23, 1986Assignee: Signetics CorporationInventor: Raymond G. Donald
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Patent number: 4616190Abstract: A steering circuit (10) in a differential amplifier having a pair of differentially arranged input amplifiers (A1 and A2) steers current from a pair of current sources (11 and 12) in such a way as to enhance slew rate without increasing offset voltage. The steering circuit is formed with a pair of steering amplifiers (A3 and A4) arranged in a differential configuration through a pair of resistors (R3 and R4).Type: GrantFiled: September 3, 1985Date of Patent: October 7, 1986Assignee: Signetics CorporationInventor: Rudy J. van de Plassche
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Patent number: 4612257Abstract: A structure for an electrical interconnection suitable for a semiconductor integrated circuit is made by a process utilizing selective tungsten deposition at low pressure to form an intermediate conductive layer without significantly ablating nearby insulating material.Type: GrantFiled: October 9, 1984Date of Patent: September 16, 1986Assignee: Signetics CorporationInventor: Eliot K. Broadbent
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Patent number: 4608585Abstract: In an EEPROM memory cell of the kind which relies on tunneling action through a thin oxide layer to store charge on a floating gate, the floating gate and the channel regions of the memory cell are provided with additional doping of the same kind as in the substrate in order to raise the virgin state threshold voltage of the memory cell to a high positive value, such as 4 volts. Additionally, the overlap area between the control gate and the floating gate is reduced to the extent that the capacitance between the floating gate and the control gate is substantially equal to the capacitance between the floating gate and the substrate during programming, but the effective capacitance between the floating gate and the substrate is greatly reduced during erase mode. As a result, little or no tunneling occurs during programming and the threshold voltage level is the same as the virgin threshold value of the memory cell.Type: GrantFiled: July 30, 1982Date of Patent: August 26, 1986Assignee: Signetics CorporationInventor: Parviz Keshtbod
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Patent number: 4608588Abstract: A semiconductor device contains first and second semiconductive regions (43 and 78) and first, second, and third semiconductive zones (59/61, 79, and 71) of opposite conductivity type to the regions. The first zone adjoins an insulating layer (45/46/47/48/63) along an upper surface of the first region. The second region extends to the upper surface through a window in the insulating layer. The second zone adjoins the second region below the window and is spaced apart from the third zone which extends to the upper surface. The zones and insulating layer upwardly and laterally enclose the second region. A first segment (59) of the first zone is continuous with the third zone and at least partly adjoins the lateral edge of the insulating layer located apart from the window.Type: GrantFiled: August 23, 1985Date of Patent: August 26, 1986Assignee: U.S. Philips CorporationInventors: Michel X. M. de Brebisson, Marc Tessier
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Patent number: 4594769Abstract: A structure having substantial surface evenness is created by a method in which an insulating layer (24) that has an upward protrusion (26) is formed on a patterned conductive layer (20) having a corresponding upward protrusion (22). A further layer (28) having a generally planar surface is formed on the insulating layer. Using an etchant that attacks the further layer much more than the insulating layer, the further layer is etched to expose at least part of the insulating protrusion. The further layer and the insulating layer (as it becomes exposed) are then etched with an etchant that attacks both of them at rates not substantially different from each other. This brings the upper surface down without exposing the conductive layer, particularly its upward protrusion.Type: GrantFiled: June 15, 1984Date of Patent: June 17, 1986Assignee: Signetics CorporationInventor: Russell C. Ellwanger
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Patent number: 4593210Abstract: A bipolar gate has an output transistor (Q5) that switches in response to the voltage at an emitter of a drive transistor (Q2 or Q10). An active pull-off circuit (14) discharges the base of the output transistor (Q5) when it turns off. The discharge path is provided through a pull-off transistor (Q7) whose collector is coupled to the base of the output transistor. The switching of the pull-off transistor is regulated with a control circuit containing a trigger circuit and a bias circuit. The trigger circuit is coupled between the bias circuit and a collector of the drive transistor. A "kicker" circuit formed with an input transistor (QC1) and a voltage reference (18) speeds up the switching of the drive transistor.Type: GrantFiled: August 1, 1983Date of Patent: June 3, 1986Assignee: Signetics CorporationInventor: Richard M. Boyer
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Patent number: 4584490Abstract: A bipolar input circuit for regulating the current/voltage level at the base of a switching transistor (QA) provides a capacitively-controlled discharge path from the base through a discharge transistor (QC) when an input signal (V.sub.I) makes certain voltage transitions. The base of the switching transistor responds to the voltage at an emitter (E1) of an input transistor (QB) which has another emitter (E2) coupled to the base of the discharge transistor. Its base is further coupled to a capacitor (C) which controls the discharge path.Type: GrantFiled: March 30, 1984Date of Patent: April 22, 1986Assignee: Signetics CorporationInventor: Jeffrey A. West
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Patent number: 4578602Abstract: A bipolar signal translator contains a pair of transistors (Q1 and Q2) arranged as a current mirror with their emitters coupled to a voltage supply (V.sub.EE) by way of a pair of impedance elements (R4 and R5) that improve stability. Their collectors are coupled through another pair of impedance elements (R1 and R2) to an input transistor (Q4 or Q5) and to a device circuit (D1 and D2, D3 and D4, or Q4). The collector of one of the current-mirror transistors (Q2) is coupled to the base of an output transistor (Q3) whose collector is preferably coupled through an output impedance element (R3) to a current-control transistor (Q6) that improves power utilization.Type: GrantFiled: July 11, 1983Date of Patent: March 25, 1986Assignee: Signetics CorporationInventors: Jeffery A. West, Thomas D. Fletcher