Abstract: A device for testing continuity and current leakage at leads of an electronic circuit such as an integrated circuit has a contact structure (16) having test terminals (T1-T28) for contacting the leads. A first and a second of the leads are power supply leads respectively contactable with a first and a second of the test terminals (T14 and T28 or T26). Continuity/leakage detection is done with one or more corresponding detection circuits (D1-D28). Each detection circuit has a channel along which both continuity and leakage are tested. A supply switching circuit (26) appropriately switches voltages between values suitable for continuity testing and values suitable for leakage testing.

Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor impurity is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction laterally bounded by the island's side boundaries. A highly resistive amorphous semiconductive layer (58) which is irreversibly switchable to a low resistive state is deposited above the region in such a manner as to be electrically coupled to the region. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

Abstract: An ISL structure is fabricated by a process in which impurities are introduced into a semiconductor substrate (10) of first type conductivity (P) to form major and minor portions (18 and 18a) of a first region of opposite second type conductivity (N). The minor portion has a lower net impurity concentration than the major portion and extends to a considerably lesser depth. An impurity is introduced into the major and minor portions to form a second region (24) of first type conductivity. An impurity is introduced into the second region to form a third region (30) of second type conductivity spaced laterally apart from the minor portion. Metallization is then performed to create at least one Schottky rectifying contact (32) with the major portion and ohmic contacts (38, 36, and 34) with the substrate and second and third regions.

Abstract: A differential amplifier operable between a pair of supply voltages that define a rail-to-rail supply range contains a pair of differential portions (20 and 22) that together provide representative signal amplification across the supply range, although neither differential portion individually does so. A current control (24) regulates operating currents (I.sub.N and I.sub.p) for the differential portions in such a way that the amplifier transconductance can be controlled in a desired manner as the common-mode part (V.sub.CM) of the amplifier input signal (V.sub.I+ and V.sub.I-) varies across the supply range. The transconductance is typically controlled to be largely constant. A summing circuit (26) selectively combines internal currents (I.sub.A, I.sub.B, I.sub.C, and I.sub.D) from the differential portions to generate at least one output signal (I.sub.O+ and I.sub.O-) representative of the input signal.

Abstract: A bipolar impedance buffer contains an input transistor (Q1) whose emitter is coupled to that of a like-polarity intermediate transistor (QN). Its collector is coupled to the base of a like-polarity output transistor (QO), while its base is coupled to the collector of an opposite-polarity transistor (QP). A resistor (RN) coupled between the base and collector of the intermediate transistor significantly reduces the output settling time.

Abstract: A voltage reference for providing a reference voltage (V.sub.AB) between a pair of terminals (A and B) contains a diode (D) and a bipolar transistor (Q) whose base is coupled to one electrode of the diode. The collector of the transistor is coupled to a node (C) between one of the terminals (A) and the other electrode of the diode. The emitter of the transistor is coupled to the other terminal (B).

Abstract: A differential amplifier circuit contains a pair of complementary input portions (3, 5 and 4, 6). The input portions amplify a common differential input signal to produce corresponding amplified differential signals which are supplied to a summing section that operates as a modulated current mirror to produce an output signal representative of the input signal. The summing section contains a pair of like-polarity first and second amplifiers (13 and 14) and a pair of like-polarity third and fourth amplifiers (19 and 20) complementary to the other amplifiers. A pair of impedance elements (11 and 12) are coupled between a first voltage supply (ground reference) and the third and fourth amplifiers. A pair of current sources, typically impedance elements (8 and 9), are coupled between a second voltage supply (+B) and the first and second amplifiers.

Abstract: A non-volatile memory cell (20) contains a pair of cross-coupled like-polarity FET's (Q1 and Q2) that serve as a volatile location (21) for storing a data bit and a like-polarity variable-threshold insulated-gate FET (Q3) that serves as a non-volatile storage location (22). The variable-threshold FET has its source coupled to the drain of one of the cross-coupled FET's, its insulated-gate electrode coupled to the drain of the other of the cross-coupled FET's, and its drain coupled to a power supply. A pair of impedance elements (R1 and R2) are coupled between the drains of the cross-coupled FET's, respectively, on one hand and the power supply on the other hand. Just before a power shutdown which causes the data bit to evaporate, the power supply is pulsed to a suitable level to cause the bit to be transferred to the non-volatile location. When power is restored to the normal level, the original data bit automatically returns to the volatile location.

Abstract: A signal translator for converting an input voltage (V.sub.I) into an output voltage (V.sub.O) at a different level contains a primary element stack (10) and a similarly-configured image element stack (12), both coupled between the sources of a potentially first variable supply voltage (V.sub.CC) and a normally constant second supply voltage (V.sub.EE). A reference voltage (V.sub.R) is supplied to both a primary-stack transistor (Q2) which provides the output voltage and an image-stack transistor (Q4) which provides a feedback signal (V.sub.F). A feedback circuit (14) formed with an amplifier (16) and a shifting circuit (18) response to the feedback signal to supply the reference voltage at such a value as to compensate the output voltage for changes in the first supply relative to the second supply voltage is particularly useful for CTL-to-TTL logic.

Abstract: A bipolar differential amplifying circuit contains a pair of input transistors (3 and 4) for receiving a differential input signal, a pair of differentially-configured first and second transistor circuits (5 and 6) coupled to the input transistors, and a subtracting circuit (11 and 12) for comparing the sum of the currents through first collectors (5C.sub.1 and 6C.sub.1) of the transistor circuits with the current through a second collector (6C.sub.2) of the second transistor circuit to generate an output signal representative of the input signal. A PN diode (13) is coupled to a second collector (5C.sub.2) of the first transistor circuit. The voltages at the collectors are very close, thereby yielding a high common-mode rejection ratio for the input signal.

Abstract: A structure for an electrical interconnection suitable for a semiconductor integrated circuit is made by a process utilizing selective tungsten deposition at low pressure to form an intermediate conductive layer without significantly ablating nearby insulating material.

Abstract: A TTL circuit having a pair of current sources (R2/V.sub.CC and R2/V.sub.CC) and a pair of transistors (Q1 and Q2) arranged in a standard TTL input/inverting configuration has hysteresis at the input signal (V.sub.X) for providing noise protection. A hysteresis circuit (10) suitably containing another current source (R3/V.sub.CC) coupled to the base of the inverting transistor (Q2) and a rectifier (12) coupled between the collector of the inverting transistor and the current source (R1/V.sub.CC) coupled to the base of the input transistor (Q1) provides the hysteresis at the circuit switching points.

Abstract: A film of titanitum-tungsten nitride is used to provide the dual function of a fuse link between a semiconductive device and an interconnect line in a memory array and of a barrier metal between another metal and a semiconductor region.

Abstract: A method of manufacturing a semiconductor device having two juxtaposed regions (12, 16) of opposite conductivity types which adjoin a surface and which together constitute a p-n junction (9) which is preferably perpendicular to the surface and the doping concentration of which decreases towards the surface. According to the invention n-type and p-type buried layers (2, 6) are provided beside each other on a semiconductor substrate (1) and on said layers a high-ohmic epitaxial layer (7) is grown. By heating, the dopants diffuse from the buried layers through the whole thickness of the epitaxial layer and into the substrate. With suitably chosen donor and acceptor atoms (for example boron and phosphorus in silicon) n and p-type regions (12, 16) are formed in the epitaxial layer and form a p-n junction (9) perpendicular to the surface by compensation of the lateral diffusions from the buried layers.

Abstract: A MOS power-on reset circuit includes Schmitt trigger circuit and an inverter. The Schmitt trigger circuit comprises first, second, and third depletion transistors serially connected between reference potential and supply voltage. The first and second depletion transistors are connected at a first junction point, and the second and third depletion transistors are connected at a second junction point. The gates of the first and second depletion transistors are commonly connected for receiving an input substrate bias voltage. An enhancement transistor is connected between the first junction point and supply voltage. The gates of the enhancement transistor and the third depletion transistor are commonly connected to the second junction point, which is the output of the Schmitt trigger circuit and which is coupled to the inverter from which the output voltage is taken.

Abstract: A read resettable memory circuit contains a flip-flop circuit (10) consisting of a flip-flop (FF) and an edge-triggered control circuit (CC) and a fall-through latch (16). The control circuit sets the flip-flop in response to a selected edge transition in a first clock (.0..sub.1) when an appropriate external logical set signal (S) is received and resets the flip-flop in response to a selected edge transition in a second clock (.0..sub.2) when an appropriate feedback logical reset signal (R) is received. The latch provides the reset signal at a value corresponding to the current logic state of the flip-flop during each period running from the selected edge transition of the second clock to its opposite edge transition and at a value corresponding to the logic state of the flip-flop that exists just before each opposite edge transition of the second clock during each remaining following period.

Abstract: A semiconductor device is fabricated by a process in which an aperture (4) is an insulating layer (3) along a surface (2) of a semiconductor body is utilized in defining the lateral extents of zones (6, 7, and 8) in a circuit element of the device. In particular, the insulating layer is first provided with the aperture along the surface. A semiconductor layer (5) is formed on the insulating layer, including the portion within the aperture. Using the edge of the insulating layer along the aperture as a masking edge, a pair of opposite-conductivity dopants are introduced selectively into the aperture and a third dopant is introduced through all of the aperture into the body. The third dopant may be introduced into the body before the semiconductor layer is formed.

Abstract: The edge profile of a silicon layer is shaped to have a gradual incline considerably less than 90.degree. by continuously reducing the amount of oxygen mixed with carbon tetrachloride in a reactive ion etching environment. The etching mode varies from complete isotropic etching when the amount of oxygen is maximum, to complete anisotropic etching when the oxygen content is zero.

Abstract: A logic circuit in which (1) a first bipolar transistor has a base, an emitter, and a collector coupled to a voltage/current source, and (2) a second bipolar transistor has a base coupled to the emitter of the first transistor, an emitter coupled to a constant voltage source, and a collector coupled to the voltage/current source contains operational control circuitry for preventing the second transistor from either turning off or normally going into deep saturation. Each transistor is typically an NPN device. The operational control circuitry may then comprise (1) first circuitry for providing current from the voltage/current source in a single current-flow direction to the collector of the second transistor and (2) second circuitry for providing current from the first circuitry in a single current-flow direction to the base of the second transistor. Optimally, the first circuitry prevents the second transistor from ever going into deep saturation.

Abstract: A method of manufacturing integrated circuits by means of a multilayer mask.Etching of the layers of the mask comprises a lateral etching of the bottom layer so that at the edge of the auxiliary layer edges appear which are removed partly prior to forming an insulating layer and partly after the formation thereof, after which a remainder of a mask portion is also removed as a result of which removal apertures for the formation of zones are determined.