Patents Represented by Attorney Rabin & Berdo, P.C.
  • Patent number: 7650989
    Abstract: A loose-leaf article placing structure is composed primarily of an unfoldable board, on which is crossly divided into four leaves. Each leaf is provided with an article emplacement seat, three linked loose-leaves are located among the four leaves, the first leaf is separated from the last leaf, and the loose-leaves are deployed as that one leaf is folded inward with the other one being folded outward, alternately. Accordingly, when the board is folded, the four leaves will be overlapped, such that every two article emplacement seats are facing toward each other to facilitate placing the articles as a kit, so as to save packaging cost and increase product texture, while at a same time, with a surface of the board also directly providing for posting a printed show page.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: January 26, 2010
    Inventor: Ta-Pan Chou
  • Patent number: 7651447
    Abstract: A strike trainer has an attachment assembly, a shock absorber, a target mount and a target. The attachment assembly has an attachment body, an outer stabilizer being mounted on the attachment body, a metal sleeve being mounted through the attachment body and the outer stabilizer and an inner stabilizer being formed inside the metal sleeve. The shock absorber is connected to the metal sleeve of the attachment assembly. The target mount is mounted in the shock absorber and has an inner disk, an outer disk, a metal sleeve and a plastic tube being mounted inside the metal sleeve. The outer disk is mounted on an outer surface of the inner disk, the metal sleeve of the target mount is mounted through the inner and outer disks and the plastic tube is mounted in the metal sleeve. The target is mounted on the target mount.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: January 26, 2010
    Assignee: Chuang Yii Enterprise Co., Ltd.
    Inventor: Chui-Ching Yang
  • Patent number: 7652985
    Abstract: A data transmission system and method and a method of selecting a communication path for a dual-controller system are provided, which are applied in a first controller and a second controller of the dual-controller system. First of all, a corresponding transmission medium is selected according to a feature of a data request issued by a controller, then the data request is converted into a data format compatible with a medium interface corresponding to the selected transmission medium and is sent to a corresponding medium driving portion connected with the medium interface, and the data request is sent to another controller through the medium driving portion and a connected corresponding medium controller, so as to select a path of the highest transmission performance, and realize the data transmission between the two controllers.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: January 26, 2010
    Assignee: Inventec Corporation
    Inventors: Xiang-Bin Meng, Tom Chen, Win-Harn Liu
  • Patent number: 7652324
    Abstract: A NAND type dual bit nitride read only memory and a method for fabricating thereof are provided. Firstly, a plurality of isolation layers, which are spaced and parallel to each other are formed in the substrate. Next, a plurality of word lines and a plurality of oxide-nitride-oxide (ONO) stack structures are formed on the substrate. The word lines are spaced and parallel to each other, and also the word lines are perpendicular to the isolation layers. Each of the ONO stack structure is located between the corresponding word line and the substrate. And then a plurality of discontinuous bit lines, which are located between the word lines and between the isolation layers are formed on the substrate. The structure of the present invention of the NAND type dual bit nitride read only memory is similar to that of a complementary metal-oxide semiconductor (CMOS), and their fabrication processes are fully compatible.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: January 26, 2010
    Assignee: Macronix International Co., Ltd.
    Inventor: Chien-Hung Liu
  • Patent number: 7651937
    Abstract: A bumping process and a structure thereof are provided. The bumping process includes the following steps. Firstly, a wafer having a number of pads is provided. Next, a UBM layer is formed on the pad. Then, a conductive first photo-resist layer is coated on the wafer to cover the UBM layer. Next, a second photo-resist layer is coated on the first photo-resist layer. Then, at least a portion of the second photo-resist layer is removed to form an opening above the UBM layer. The first photo-resist layer maintains electric connection with the UBM layer. Next, a solder layer is formed in the opening by electroplating process. Then, the first photo-resist layer and the second photo-resist layer are removed expect the portion of the first photo-resist layer under the solder layer.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: January 26, 2010
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chueh-An Hsieh, Li-Cheng Tai, Shyh-Ing Wu, Shih-Kuang Chen
  • Patent number: 7645515
    Abstract: A transfer arrangement is used in a transfer portion of an image forming apparatus. The transfer arrangement includes an electrically conductive member that contacts a toner image bearing member of the image forming apparatus. The electrically conductive member is made of polyurethane resin to which electrically conducive polymer is added. An adding amount of the electrically conductive polymer with respect to the polyurethane resin is from 8 wt % to 40 wt %.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: January 12, 2010
    Assignee: Oki Data Corporation
    Inventors: Satoru Furuya, Mitsuru Kishimoto
  • Patent number: 7646951
    Abstract: Provided is an apparatus for manufacturing an optical fiber Bragg grating.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: January 12, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Joon Tae Ahn, Hong Seok Seo, Bong Je Park
  • Patent number: 7647566
    Abstract: A method for creating new vias in an integrated circuit chip. The method automatically creates a plurality of new vias around an original via for electrically connecting two metal layers to each other in circuit layout data of the integrated circuit chip. The new vias also electrically connect the two metal layers to each other. According to the new vias, the probability of certainly electrically connecting the two metal layers of the integrated circuit chip to each other can be increased when the integrated circuit chip is being manufactured.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: January 12, 2010
    Assignee: Himax Technologies Limited
    Inventor: Shih-Yi Su
  • Patent number: 7647395
    Abstract: A terminal management system includes a terminal apparatus connected to a local network, a management server capable of transmitting and receiving information relating to the terminal apparatus through the local network, and a client terminal capable of receiving the information relating to the terminal apparatus from the management server through the local network. The management server includes a terminal searching section for searching for the terminal apparatus connected to the local network, a terminal information transmitting section for transmitting information relating to this terminal apparatus to the client terminal with reference to information relating to the client terminal, and a driver requesting section for requesting a data server connected to an external network for a driver program for operating the terminal apparatus, in accordance with request information transmitted from the client terminal. The management server transmits an installer and the driver program to the client terminal.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: January 12, 2010
    Assignee: Oki Data Corporation
    Inventor: Keiichi Sando
  • Patent number: 7646318
    Abstract: Provided is an H.264 Context Adaptive Variable Length Coding (CAVLC) decoding method based on an Application-Specific Instruction-set Processor (ASIP). The H.264 CAVLC decoding method includes determining a plurality of comparison bit strings on the basis of a table of a decoding coefficient, storing lengths of the comparison bit strings in a first register, storing code values of the comparison bit strings in a second register, comparing an input bit stream with the comparison bit strings based on the lengths and code values of the comparison bit strings, and determining value of the decoding coefficient according to a result of comparison between the input bit stream and the comparison bit strings. The method extracts a decoding coefficient using a register in an ASIP without accessing a memory and prevents a reduction in speed caused by memory access, thereby increasing the decoding speed of an H.264 decoder.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: January 12, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae Jin Lee, Jun Young Lee, Moo Kyoung Chung, Seong Mo Park, Nak Woong Eum
  • Patent number: 7646499
    Abstract: An authentication code detecting unit detects data addition authentication information from a print job. An upper apparatus specifying unit specifies a transmitting source of the print job. A RAM stores the data addition authentication information, the transmitting source of the print job, and the print job. An operating unit receives print request authentication information. An elapsed time measuring unit measures an elapsed time from the reception of the print job having the data addition authentication information. An erasure extension necessity inquiry unit requests an answer about the necessity of extension of an erasing time from the transmitting source when the measurement result indicates the elapse of a predetermined time. When the erasure extension is necessary, an erasure/extension decision processing unit extends the elapsed time until the erasure of the print job after its reception.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: January 12, 2010
    Assignee: Oki Data Corporation
    Inventor: Masafumi Hayakawa
  • Patent number: 7646583
    Abstract: A common centroid symmetric structure capacitor is provided, which includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer. The first metal layer is adjacent to the second metal layer, the third metal layer is adjacent to the first metal layer, the fourth metal layer is adjacent to the second metal layer, and the first metal layer is symmetric to the fourth metal layer, the second metal layer is symmetric to the third metal layer. Each of the metal layers has two sets of metal wires, each set has a plurality of metal wires, and each of the metal wires in each set is arranged in an interlaced manner.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: January 12, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Szu-Kang Hsien, I-Hsun Chen, Chien-Hua Cheng
  • Patent number: 7643280
    Abstract: The assembling structure for electronic module comprise a case and a side frame, the characteristic is the case fixed on the base frame of the assembling structure by two front pivots and the case pivoted thereon. Besides, the side frame is installed adjacent to the case. In addition, the case and the side frame respectively include a plurality of locking holes, the side frame further including a locking controller with a first latch and a second latch corresponding to the locking holes, thereby locking the case at a horizontal and oblique position.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: January 5, 2010
    Assignee: First International Computer, Inc.
    Inventor: Chiang-Ko Chen
  • Patent number: 7642595
    Abstract: There are provided a nonvolatile semiconductor memory of a structure in which electric signals from peripheral circuits are reliably transferred to control gates via word lines even if contact holes cannot be opened accurately above the word lines, and a method of fabricating the nonvolatile semiconductor memory. Plural word lines and plural bit lines are disposed on a semiconductor substrate, and there are memory cells at intersecting portions of the word lines and the bit lines. At contact portions of the word lines and metal wires of an upper layer, polysilicon regions, which include the contact portions, are formed beneath a polysilicon forming the word lines, as an etching stop layer at a time of forming contacts.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: January 5, 2010
    Assignee: OKI Semiconductor Co., Ltd.
    Inventor: Masaru Seto
  • Patent number: 7641935
    Abstract: The present invention is method of liquid crystal alignment for a flexible LCD with micro-grooves comprising: coating a thermoplastic material onto a conductive film; heat embossing a plurality of micro-grooves formed by a mold, wherein the surface of said mold forms said plurality of micro-grooves; and aligning said plurality of micro-grooves with an aligning wall and grooves. The present invention also adds a plurality of liquid alignment technology in roll-to-toll micro cell LCD processes. The plurality of liquid alignment technology lets the micro cells of the LCD from without aligning with an alignment LCD mode (such as TN, VA or horizontal alignment) and achieves a better contrast and display quality.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: January 5, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Kang-Hung Liu, Chi-Chang Liao, Ching-Hsiang Chan, Yu-Chu Hung
  • Patent number: 7643432
    Abstract: A method for analyzing a network environment, is provided. First acquiring a plurality of connection data of all network cards of a terminal device is performed. Then, according to connection data, determining whether or not a terminal device uses a PPPoE connection to connect to a network system. Finally, determining whether or not an IP address of the terminal device is a public IP address and determining whether or not the terminal device uses DHCP to acquire a target IP address.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: January 5, 2010
    Assignee: Vivotek Inc.
    Inventors: Jen-Chih Wu, Sheng-Fu Cheng, Jung-Jen Lee, Nai-Wen Huang, Shih-Wu Fan-Jiang, Yen-Chun Liao
  • Patent number: 7643337
    Abstract: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: January 5, 2010
    Assignee: Macronix International Co., Ltd.
    Inventors: Yung-Feng Lin, Nian-Kai Zous, I-Jen Huang, Yin-Jen Chen
  • Patent number: D607479
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: January 5, 2010
    Assignee: DXG Technology Corp.
    Inventor: Tzu Chiang Yu
  • Patent number: D608384
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: January 19, 2010
    Inventor: Kai Alex Tang
  • Patent number: D608667
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: January 26, 2010
    Inventor: Chin-Feng Chang