Abstract: An arrangement and method for compensating for the written-in tracking error for a linear tape drive filters out spatial error components of a position error signal (PES). The position information contained within A, B pairs of servo stripes, and within C, D pairs of stripes is preserved. The timing between the A and C bursts and the C and A bursts is filtered, such as by low pass filtering, to filter out the error that can be written-in by a servo writer. The timing signal for the A, B bursts and C, D bursts are divided by the filtered timing signals for the AC and CA timing signals, respectively. This ratio provides the filtered PES signal used by a head positioner to precisely position the head with respect to the tape.

Abstract: A strut (10) for hooking an engine (16) under a wing body assembly (12) of an aircraft comprises a rigid structure as well as a mechanism for hooking this structure under the wing body assembly. This mechanism comprises a front fastener (22), a rear fastener (24) and a structure (26) for absorbing thrust. To install an engine (16) of greater diameter under the wing body assembly (12) of an existing plane, the rear part (20b) of the strut (10) is given a width which increases as it progresses to the rear. Furthermore, the rear fastener (24) comprises two braces which are fixed on both sides of the rigid structure and two shackles which connect each of the braces to an additional transverse rib integrated into the wing body assembly.

Abstract: The cameras (10) of this X-ray detector are all mounted on a common rigid plate (1) by a surface support and screwed to ensure their optical distance from a scintillator (7) itself mounted on the plate (1) by an enclosure (6) forming a darkroom (8). The common mounting of the principal elements of the detector on a single rigid plate thus significantly reduces image deterioration produced by deformations of the detector, of thermal or mechanical origin.

Abstract: The invention relates to a device for acquisition of measurements using a digital communication bus (10) and a computer system, comprising: a bus arbitrator (11) connected to this bus (10), with the function of acting as the bus master and which synchronizes measurements made using sensors (14), several items of slave equipment (13) connected on this bus (10), to which these sensors (14) are connected, two line termination devices; the first being integrated in the bus arbitrator (11) and the second being integrated into slave equipment (13) at the other end of the bus (10) opposite the bus arbitrator (11). The invention also relates to a measurement acquisition process.

Abstract: This invention relates to a method for detection of a shielding fault in a multiwire cable forming part of a communication network, during functional operation of the said network, the said cable (10) transferring a multiframe signal S(t), which comprises the following steps: a disturbing signal I(t) is injected into the said cable through an injection clamp (14) for a determined time T, when an item of equipment (12) receives the signal S(t), the number N of frames in fault during the injection period of the disturbing signal I(t) is counted, it is decided that there is a shielding fault in this cable if N/T?TEPmax, where TEPmax is the maximum packet error rate to be guaranteed.

Abstract: A flow control device comprises an inlet port through which fluid is supplied, an outlet port through which the fluid is delivered, a valve body which is arranged in a passage between the inlet port and the outlet port so as to open and close the passage, the flow control device further comprising a valve body guide means which urges downwardly and pulls upwardly the valve body so as to allow the fluid in the passage to flow at a flow rate which is lower than a basic control rate of the flow control device.

Abstract: Resolving timing violations introduced by a logic built-in self test (LBIST) sub-circuit formed within an underlying integrated circuit includes analyzing a circuit path-list corresponding to the integrated circuit for timing violations and generating a circuit timing violations analysis output; generating a first LBIST/circuit path-list based on the circuit path-list and an LBIST path-list corresponding to the LBIST sub-circuit; analyzing the first LBIST/circuit path-list for timing violations and generating an LBIST/circuit timing violations analysis output; comparing the LBIST/circuit timing violations analysis output with the circuit timing violations analysis output; generating an LBIST/circuit constraint file based on the comparison and predetermined protocols; and generating a second LBIST/circuit path-list based on the circuit path-list, the LBIST path-list and the constraints file. In this way, timing problems are quickly and efficiently resolved.

Abstract: An interface device and method for interfacing instruments to a medical procedure simulation system serve to interface peripherals in the form of mock medical instruments to the medical procedure simulation system computer to enable simulation of medical procedures. The interface device includes a housing having a mock bodily region of interest to facilitate insertion of a mock instrument, such as an endoscope tube, into the interface device. The mock bodily region of interest may be pivotable to simulate various patient orientations. The instrument is engaged by a capture mechanism in order to measure rotational and translational motion of the instrument. An actuator is disposed within the interface device to provide force feedback to the instrument. The measured motion is provided to the computer system to reflect instrument motion on the display during the simulation. Alternatively, the interface device may be configured to accommodate instrument assemblies having a plurality of nested instruments (e.g.

Abstract: This invention relates to a secure electronic device comprising: at least an electronic circuit (10) containing information to be protected, an energy source (11); at least one sensor (12, 13, 14) capable of measuring a determined physical magnitude and outputting a value representative of this magnitude, means (15, 16, 17) of comparing each value with at least one predefined threshold (ref1, ref2, ref3) outputting result signals, a device (20) for protection of information comprising means for triggering destruction of at least part of the circuit using pyrotechnic means (27), a decision-making logical device (21) capable of activating the protection device after seeing the result signals, firing means (31) capable of priming a local or global pyrotechnic micro-charge (30) using electrical energy permanently stored in the energy source.

Abstract: The present invention, generally speaking, uses multiple selectable power supply paths, a saturation detector, or combinations of the same to achieve efficient power supply processing. In one aspect of the invention, a power supply processing circuit includes a first switched converter stage and a second linear stage. Depending on the power supply desired, the first stage may be bypassed to avoid conversion losses. In another aspect of the invention, a saturation detector is used to control the first stage such that the second stage operates efficiently just short of saturation, thereby avoiding distortion.

Abstract: An interface device for interfacing a user with a computer, the computer running an application program and generating a graphical image and a graphical object, comprises a user manipulatable object in communication with the computer, a sensor to detect a manipulation of the object, the sensor providing a signal to the computer to control the graphical image, and an actuator adapted to provide a haptic sensation to the palm of the user in relation to an interaction between the graphical image and the graphical object, the actuator comprising a member that is deformable to provide the haptic sensation.

Abstract: A method and apparatus for checking the level of SNMP MIB support by network devices. An input text file indicating the MIB variables and their associated VALID/INVALID values is provided by the device designer. An input file is created for each NMS management application for which support is desired or required. The process includes identifying the variable, obtaining the value for the variable, and checking the value against any and all VALID/INVALID) values. If the value of any variable is found to not be valid or to be invalid, then an error message is generated. The process is repeated with each MIB variable in the input file provided by the device designer. After the input file is empty, one or more output files for each NMS management application for which support has been checked is generated.

Abstract: An etch processor for etching a wafer includes a chuck for holding the wafer and a temperature sensor reporting a temperature of the wafer. The chuck includes a heater controlled by a temperature control system. The temperature sensor is operatively coupled to the temperature control system to maintain the temperature of the chuck at a selectable setpoint temperature. A first setpoint temperature and a second setpoint temperature are selected. The wafer is placed on the chuck and set to the first setpoint temperature. The wafer is then processed for a first period of time at the first setpoint temperature and for a second period of time at the second setpoint temperature.

Abstract: A device for controlling a continuous movement of an object with symmetry of revolution (1) comprises a conveyor (5) having two parallel guides, (6) and at least one pair of belts (8) stretched on the guides, between and on which these objects move at the level of the guides. These belts form an angle (11) between a top track and a lower track of each of the belts. The belts in the pair have the same direction of rotation around the guides, the same value of the measured angle (11) from the upper track to the lower track, and the same displacement speed. Preferably, the pair of belts consists of a single folded belt.

Abstract: A plasma processing system having a grounded chamber and an RF power feed connected to a bottom electrode is tested. A first capacitance between the bottom electrode and the grounded chamber is measured at atmosphere. Consumable hardware parts are installed in the chamber. A second capacitance between the bottom electrode and the grounded chamber is measured at vacuum with the grounded chamber including all of the installed consumable hardware parts. The first capacitance measurement and the second capacitance measurement are respectively compared with a first reference value and a second reference value to identify and determine any defects in the plasma processing system. The first and second reference value respectively are representative of the capacitance of a defect-free chamber at atmosphere and the capacitance of a defect-free chamber including all of the installed consumable hardware parts at vacuum.

Abstract: In order to direct content requests to an appropriate content serving site in a computer network, a phased learning approach is utilized to ensure that, as best as possible, the request is made to content serving site with the shortest delay. In a setup phase, an indirect path return geographic sever load balancer times sends transit time requests to all of the individual content serving sites so that the transit requests all arrive at the content serving sites at the same time. Therefore, when the requesting fixed location receives communications from the content serving sites, it can easily tell which content serving site has the least delay by an established race condition. The winner of the race may then be relayed to the indirect path return geographic server load balancer for later usage. In an execution mode, only the m fastest content serving sites and n other sites (used to test random and new sites) are sent a transit time request when a DNS request arrives from the requesting fixed location.

Abstract: A group of network devices, such as Ethernet switches, are logically configured as a single cluster, with one commander device and one or more member devices. Each network device in the cluster contains an embedded HTML server that facilitates configuration and management of the network device via a management station running a Web browser. Each device in the cluster is identified by a unique Universal Resource Locator (“URL”). However, only the cluster commander is required to have a public IP address. The cluster commander automatically assigns private IP addresses to the other devices in the cluster. Network devices in the cluster constantly monitor network traffic on all their ports to detect conflicts between the automatically assigned IP addresses and the IP addresses of network devices outside of the cluster. When a conflict is detected, the cluster commander assigns a different private IP address to the cluster network device that caused the conflict.

Abstract: Certain bits of a packet, such as bits in the IP header of an IP packet, are used to designate the type of service or Quality of Service (QoS) level to be afforded to the packet as it passes through a data communications network. A user entitled to a certain QoS level logs into a service selection gateway SSG. The SSG queries an authentication, authorization and accounting (AAA) server in response to a log-in attempt by the user. Upon authorization, the AAA server returns an access accept signal in addition to an indication from the user's service profile (user profile) as to the QoS level to be afforded the user. While the user is logged in, all packets are routed through the SSG. The SSG sets the certain bits of the packet in accordance with the user's assigned QoS level so that as the packets are routed through the data communications network, they are consistently afforded the assigned Quality of Service level.

Abstract: A light signaling device related to the operating state of a system has at least one light and circuits of detection of a failure of this or these lights, in which each light comprises m branches in parallel each composed of n light emitting diodes in series, and a branch selector; where m and n are integers such that m?2 and n?1. This invention also relates to a process for management of such device.

Abstract: A high reliability computer system includes a first processing engine (PE), a first memory and a third memory both accessible by the first PE, a second PE, and a second memory and a fourth memory both accessible by the second PE. The first memory contains initialization information for the first PE. The third memory has a location for storing an enable password or a surrogate therefor for the first PE. The second memory contains initialization information for the second PE. The computer system also includes circuitry for switching control of the system from the first PE to the second PE upon detection of a failure of the first PE, and a password passer writing the enable password or a surrogate therefor of the first PE to the fourth memory. Alternatively, a network system includes an authentication, authorization and accounting (AAA) or any other password server having a database for maintaining an enable password for a high reliability computer system.