Abstract: Portable communication equipment having a virtual display including display electronics and optics for providing a virtual image in the display, a virtual control panel image viewable in the virtual display as a portion of the virtual image and cursor electronics connected to the display electronics for producing a manually controllable cursor virtual image in the display. The virtual image control panel is connected to be operable with the cursor virtual image and further connected to operate the portable communication equipment. Manual controls, connected to the cursor electronics for controlling the position and function of the cursor virtual image, are mounted on the portable communication equipment and externally accessible by an operator.

Abstract: A circuit (100) has a pull-up transistor (110), a pull-down transistor (120), an input driver (200). The pull transistors (110, 120) pull an output line (102) to first or second reference lines (101, 103). The output line (102) can assume a potential higher than the potential at the first reference line (101). The circuit (100) further comprises protection transistors (150, 160, 170, 180). The protection transistors compare the potential at the output line (102) with the potential at the first reference line (101). The protection transistors keep a substrate line (106) of the pull-up transistor (110) at the potential of the output line (102) or at the potential of the first reference line (101), whichever is higher.

Abstract: A high frequency bipolar transistor (30, 60) having reduced capacitance and inductance is formed over a substrate (61). The substrate (61) is heavily doped to form a low resistance current path. A lightly doped epitaxial layer (62) isolates the substrate (61) from layers which form the transistor. The epitaxial layer (62) is the same conductivity type as the substrate (61). A topside substrate contact (73) couples an emitter of the transistor (60) to the substrate (61). The backside of the substrate (61) is metalized and conductively attached to a leaded flag of a leadframe (51) thereby eliminating wirebond inductance in the emitter of the transistor.

Abstract: A control circuit (52) for controlling power supplied to an igniter element (54), includes a first input (70) for receiving an encoded input signal generated in response to the initiation of a firing mode and a diagnostic mode. The encoded input signal comprises a code portion (100) having at least two pulses, and a power portion (102). Logic circuitry (74) determines whether the code portion (100) is valid, the code portion (100) being determined valid when it meets predefined conditions within a predetermined time window, and provides an unlocking signal (Sfire) at an output (76) when the code portion (100) is determined to be valid. A switch (78), which has a control input coupled to the output (76) of the logic circuitry (74), is enabled on receipt of the unlocking signal so that power at the first input (70) of the control circuit (52) is supplied to the output of the switch for energizing the igniter element (54).

Abstract: An apparatus and method is provided with hysteresis for switching a load according to an input signal. There is a transfer gate for transferring a first signal to a second signal. A controller receives the first signal and the second signal and provides a control signal for the transfer gate. The control signal enables the transfer gate if the first signal reaches a first magnitude and disables the transfer gate if the first signal reaches a second magnitude. The control signal is obtained from a voltage divider across the first signal. A portion of the voltage divider is shorted out by a switch activated by a second signal. Thus, the control signal depends on the second signal. The apparatus is entirely powered by the second signal.

Abstract: A chemical sensor (10) is formed in part by depositing a stack of dielectric and resistive layers (13-15) on a support substrate (11). A cavity (17) is then formed on a substrate (16) to provide thermal isolation to the chemical sensor (10). The stack of dielectric and resistive layers (13-15) is then bonded to the substrate (16) and the support substrate (11) is removed. A layer of chemical sensing material (30) is then formed on the uppermost dielectric layer (15). Openings (33) may be formed through the stack of dielectric and resistive layers (13-15) to further enhance the thermal isolation of the chemical sensor (10) from the substrate (16).

Abstract: A light emitting diode display package and method of fabricating a light emitting diode (LED) display package including a LED array display chip, fabricated of an array of LEDs, formed on a substrate, having connection pads positioned about the perimeter of the LED array display chip, a separate silicon driver chip having connection pads routed to an uppermost surface, positioned to cooperatively engage those of the display chip when properly registered and interconnected using wafer level processing technology. The display chip being flip chip mounted to the driver chip and having a layer of interchip bonding dielectric positioned between the space defined by the display chip and the driver chip. The LED display and driver chip package subsequently having selectively removed the substrate onto which the LED array was initially formed, thereby exposing the connection pads of the display chip and a remaining indium-gallium-aluminum-phosphide (InGaAlP) epilayer.

Abstract: A method of fabricating submicron HFETs includes forming a buffered substrate structure with a supporting substrate of GaAs, a portion of low temperature AlGaAs grown on the supporting substrate at a temperature of approximately 300.degree. C., a layer of low temperature GaAs grown on the portion AlGaAs layer at a temperature of 200.degree. C., a layer of low temperature AlGaAs grown on the GaAs layer at a temperature of 400.degree. C., and a buffer layer of undoped GaAs grown on the second AlGaAs layer. Complementary pairs of HFETs can be formed on the buffered substrate structure, since the structure supports the operation of p and n type transistors equally well.

Abstract: An optoelectric interconnect (70) includes an optical fiber (17) coupled to a ferrule (11) and an optoelectric board (20). Metal layer (14) is disposed over a surface (12) of the ferrule (11). An optoelectric device (61) is coupled to the optoelectric board (20) using tape automated bonding tapes (47, 51). The optoelectric board (20) and the ferrule (11) are positioned adjacent each-other so that optical radiation is transmitted from the optoelectric device (61) to the optical fiber (17). The position of the optoelectric device (61) is adjusted to achieve an optimum position which is characterized by a maximum optical radiation transmitted to the optical fiber(17). Upon achieving the optimum position, two bonding strips (54, 56) are fused with the metal layer (14) on the surface (12) of the ferrule (11).

Abstract: An interconnect package (35) for interconnecting electrical system components. A first leadframe (10) having leads (11) is encapsulated within a molding compound forming a first section (36) of the interconnect package (35). The first section (36) optionally includes channels (54). A second leadframe (20) having leads (22, 23) is encapsulated within a molding compound forming a second section (37) of the interconnect package (35). The first and second sections (36 and 37, respectively) are coupled together with an adhesive material (43). An end (44) is removed from the interconnect package (35) forming an edge (50). A semiconductor chip (51) is coupled to the edge (50).

Abstract: A technique for achieving impedance transformations utilizing transmission lines has been provided. This technique involves placing additional distributed capacitance along the length of a transmission line thereby reducing the effective characteristic impedance of the transmission line. The effective wavelength for the transmission line is also reduced thereby substantially reducing the electrical length of a quarter wavelength matching network and making the transmission line practical and effective even at low frequencies.

Abstract: A circuit that separates a luminance signal and a color signal so that dot interference in a color transition area of a reproduced image is minimized. A color video signal is transmitted to an adaptive bandpass filter via a vertical carrier color signal extraction filter. An output signal from the adaptive bandpass filter represents the color signal portion of the color video signal. The color signal is subtracted from the color video signal via a subtractor circuit to produce the luminance signal portion of the color video signal. Since the output signal of the bandpass filter is subtracted from the color video signal, the luminance signal portion of the color video signal is separated without being affected by different colors before and after a color transition point.

Abstract: A differential track and hold amplifier circuit (200) is provided. The track and hold amplifier includes an input transconductance amplifier (212), an output amplifier (111), and a second transconductance amplifier (214). The track and hold circuit further includes a switching circuit (108) for coupling the output of the input transconductance amplifier to a capacitor (110) in the output stage of the track and hold circuit during track mode, and for decoupling the capacitor from the input amplifier during hold mode. The track and hold circuit further includes a subtractor circuit (103) for reducing a common mode voltage of the output of the input transconductance amplifier, thereby maintaining a stable voltage across the capacitor during hold mode. Further, during hold mode, the second transconductance amplifier acts in a negative feedback configuration to reduce the gain of the input amplifier to attenuate its output signal.

Abstract: A switchable constant gain summer circuit (10) has been provided. The summer circuit selectively amplifies a plurality of input signals while maintaining a constant dc current flowing through a load which maintains a constant gain for the summer circuit. The summer circuit includes a plurality of amplifier circuits (12, 16) being respectively responsive to a plurality of input signals wherein each one of amplifier circuits has a control input and common first and second outputs for respectively providing first and second output signals. A plurality of control means (14, 18) responsive to a plurality of control signals is included for alternately providing first and second voltages to each one of the control inputs of the amplifier circuits. A load circuit (20) is coupled to the common first and second outputs of the amplifier circuits wherein a DC bias through the load circuit is substantially constant.

Abstract: A varactor (10, 115, 122) is formed using a BICMOS process flow. An N well (28) of a varactor region (13) is formed in an epitaxial layer (22) by doping the epitaxial layer (22) with an N type dopant. A cathode region (55, 132) is formed in the N well (28) by further doping the N well (28) with the N type dopant. Cathode electrodes (91, 114) are formed by patterning a layer of polysilicon (62, 86) over the epitaxial layer (22). Subsequently, the cathode electrodes (91, 114) are doped with an N type dopant. A region adjacent the cathode region (55, 132) is doped to form a lightly doped region (103, 117). The lightly doped region (103, 117) is doped with a P type dopant to form an anode region (109, 119).

Abstract: A method of forming an insulated gate semiconductor device (10). A field effect transistor and a bipolar transistor are formed in a portion of a monocrystalline semiconductor substrate (11) that is bounded by a first major surface (12). A control electrode (19) is isolated from the first major surface by a dielectric layer (18). A first current conducting electrode (23) contacts a portion of the first major surface (12). A second current conducting electrode (24) contacts another portion of the monocrystalline semiconductor substrate (11) and is capable of injecting minority carriers into the monocrystalline semiconductor substrate (11). In one embodiment, the second current conducting electrode contacts a second major surface (13) of the monocrystalline semiconductor substrate (11).

Abstract: A circuit and method for providing phase synchronization between an ECL output signal and a TTL or CMOS output signal has been provided. The circuit includes phase locked loops (20, 24) to make the difference of delays through an ECL-TTL/CMOS translation path with that of a straight ECL path irrelevant. As a result, in order to achieve phase synchronization between an ECL signal and a TTL/CMOS signal, one only needs to match the propagation delay of a delay component (22) to that of a TTL/CMOS-ECL translator (26) as opposed to a delay component and an ECL-TTL/CMOS translator.

Abstract: An oscillator circuit with enhanced frequency characteristics is provided. This oscillator circuit includes a buffer (102) to amplify the output signal and provide a positive feedback, an inverter (106) to provide negative feedback to cause oscillation, a capacitive divider circuit (110, 112) for charge storage, a resistor (116) to provide controlled discharge, and a diode circuit (114) for providing frequency stability. Since frequency stability is included within the oscillator circuit, there may be no need to perform resistor trimming at the time of manufacture. Further, the capacitive divider circuit eliminates parasitic charge injection.

Abstract: A BIST circuit that can be placed in a halt mode has been provided. During halt, the operation of the BIST circuit is stopped when an error has been detected thereby allowing for faster location of the error. The BIST circuit also includes a memory access mode which allows for independent read or write access to a predetermined address of a storage device under test.

Abstract: A CMOS driver (10) with output feedback pre-drive has been provided. The CMOS driver includes first (14) and second (16) output devices for providing drive current at an output (18). The CMOS driver includes an output feedback pre-drive circuit (12) which includes complementary P and N feedback devices (26, 28, 30, 32) that are coupled across the gate and drain electrodes of the output devices and which are controlled by an input signal.