Abstract: An electronic device in a cavity in a mold is encapsulated by a composite plastic having two materials placed, respectively, in sequential locations in a reservoir in the mold. The first material has desirable properties when in contact with the surface of the device, e.g., better adhesion. The second and different material has other desirable properties, e.g., mechanical strength, low moisture permeability, etc. The first location is first in line in a direction through the mold chambers to the cavity. The two-part encapsulant is injected into the cavity without significant turbulence so as to avoid much mixing of the two materials. This creates a boundary layer of the first material which preferentially applies a coating to the device while the second material substantially fills the bulk of the space in the mold cavity. A composite encapsulation is formed having overall superior properties.

Abstract: A substrate having a vent (20) and a method of forming the vent (20). A substrate (11) has conductive traces (14) and a semiconductor chip attach pad (17) on a top surface and conductive traces (12) and a bonding pad (13) on the bottom surface. A masking layer (18) is formed over the substrate (11) and openings are formed in the masking layer (18) to expose the conductive traces (14) and a semiconductor chip attach pad (17). The vent (20) is formed in the masking layer (18). A semiconductor chip (31) is mounted to the semiconductor chip attach pad (17). During a step of encapsulating the semiconductor chip (31) with a mold compound, the vent (20) provides pressure relief.

Abstract: Pressure sensors that are fabricated to sense low pressures are tested and calibrated by providing a controlled gas flow or leak to create a pressure during testing. Rather than placing the pressure sensor in a sealed environment, a controlled leak of a gas is used to induce a stable and controllable pressure region over the pressure sensor during testing. The stable low pressure region is monitored via a sensing tube.

Abstract: A bandgap reference circuit (60) provides a selectable bandgap reference voltage that is substantially insensitive to temperature variations of an operating reference circuit. A final curvature caused by a current (I.sub.2) in a temperature coefficient compensation transistor (40) is equal to a drift in a Vbe voltage of a transistor (18) having a negative temperature coefficient plus the drift in a Vbe voltage of a transistor (20) having a positive temperature coefficient minus the drift in a Vbe voltage of the temperature coefficient compensation transistor (40). The nonlinearity of the current (I.sub.2) in the temperature coefficient compensation transistor (40) is adjusted by selecting a compensating current and associated temperature coefficient for the compensating current (I.sub.0) to minimize the characteristic bow or curvature of the current (I.sub.2) in the temperature coefficient compensation transistor (40).

Abstract: A ferroelectric memory array (20) monolithically integrated with a field programmable gate array (32) into a semiconductor circuit (10). The ferroelectric memory array (20) is suitable for a semiconductor manufacturer to program the configuration data that is used in the field programmable gate array (32) prior to shipment and installation in an electronic system. The memory array (20) provides the data that configures the field programmable gate array (32) for functionality of the Configurable Logic Blocks (CLBs) in the field programmable gate array (32). Should the field programmable gate array (32) circuit lose power, the non-volatile memory array (20) provides a shift register (26) with the data to reconfigure the field programmable gate array (32).

Abstract: A phase-frequency detector (12) is configured for operating at a high frequency. A transition of a clock signal (REF CLK) is detected by a first latch (52) and a signal UP is generated. A transition of a feedback signal (FBK) is detected by a second latch (56) and a signal DOWN is generated. An logic circuit (64) detects the signals UP and the DOWN and generates a reset signal (RESET). A pulse-width of the reset signal (RESET) is controlled and limited by the logic circuit (64) to provide a faster response time for setting the first and second latches (52 and 56) to a state that allows detection of the phase and frequency differences between the clock signal (REF CLK) and the feedback signal (FBK).

Abstract: A circuit and method protect a transistor (68, 70) from damage when controlling an input signal (V.sub.PROG) that exceeds a gate to channel stress voltage of the transistor. A small, low current protection transistor (64, 66) is serially coupled to the gate electrode of the transistor being protected. The gate of the protection transistor is biased to a voltage (V.sub.P, V.sub.N) of lower magnitude than the input signal to limit the voltage applied to the gate of the protected transistor to a value within the stress voltage of the protected transistor.

Abstract: A single level gate NVM device (10) includes p-channel and n-channel floating gate FETs (12, 14), an erasing capacitor (26), and a programming capacitor (28). The NVM device (10) is programmed by applying a programming voltage to the programming capacitor (28) and applying a ground voltage to the sources of the FETs (12, 14). The NVM device (10) is erased by applying an erasing voltage to the erasing capacitor (26) and applying ground voltage to the sources of the FETs (12, 14) and to the programming capacitor (28). Data is read from the NVM device (10) by sensing a voltage level at the drains of the FETs (12, 14) while applying a logic high voltage to the source of the p-channel FET (12), a logic low voltage to the source of the n-channel FET (14), and a reading voltage to the programming capacitor (28).

Abstract: A layered bismuth ferroelectric structure (12) and a method for forming the bismuth layered ferroelectric structure (12). A monolayer (12A) of bismuth is formed in intimate contact with a single crystalline semiconductor material (11). A layered ferroelectric material (12) is grown on the monolayer (12A) of bismuth such that the monolayer (12A) of bismuth becomes a part of the layered ferroelectric material (12). The ferroelectric material (12) forms a layered ferroelectric material which is not a pure perovskite, wherein the crystalline structure at the interface between the single crystalline semiconductor material (11) and the monolayer (12A) of bismuth are substantially the same.

Abstract: A process combines a high performance silicon pin diode (60) and other semiconductor devices such as transistors, resistors, and capacitors. The pin diode (60) is formed beneath an epitaxial layer (44) of the device at a depth that maximizes absorption of light having a wavelength greater than approximately 600 nanometers. Devices such as transistors are formed in the epitaxial layer (44). An integrated circuit has a substrate (41), an intrinsically doped layer (42), a buried layer (43), and an epitaxial layer (44). An isolation region (45) isolates an intrinsically doped region (46), a buried layer region (47), and the epitaxial layer region (48). The pin diode (32) has a substrate (41), an intrinsically doped region (46), and a buried layer region (47). A polysilicon region (62) provides a top side contact for the pin diode (60).

Abstract: A variable conducting element (10) and method for programming a constant current or constant resistance provided at output terminals (24 and 26) of a ferroelectric transistor (12). The ferroelectric transistor (12) has portions of a ferroelectric material (32A) programmed having up-polarization states separated by domain walls (34) from portions of a ferroelectric material (32B) programmed having down-polarization states. The portion of the ferroelectric material (32A) programmed in the up-polarization state forms current conduction channels between a source region (23) and a drain region (25) of the ferroelectric transistor (12). The ferroelectric transistor (12) is programmed through a capacitor (14) to adjust the charge supplied to a control terminal (22) of the ferroelectric transistor (12).

Abstract: An SRAM memory cell (40) uses GCMOS transistors (42, 44, 56, and 58) for improving discharge of complementary bit lines (60 and 62). The GCMOS transistors (42, 44, 56, and 58) have a graded-channel region on only the source side of the transistors. Configuring the pass-transistors (56 and 58) having the drain terminals connected to the complementary bit lines (60 and 62) and the cross-coupled transistors (42 and 44) having drain terminals connected to the memory cell outputs improves timing for a read operation of the memory cell (40).

Abstract: A semiconductor die (32) is disposed on a heat sink (22) in an electronic package (10). During assembly, a leadframe (20) is connected to the heat sink (22) by down-set tabs (14, 28), which are offset from the heat sink (22) and disposed within the boundary (19) in which the final package (10) will be molded. Individual heat sinks (22) are pre-out prior to molding the final packages (10). In one roach, pins (36) are used to connect down-set tabs (14, 28) to heat sink (22).

Abstract: Remote energy transmitting circuits 30, 35, 36, 37 sequentially transmit a first RF signal when activated by the controller 60. A remote unit 14 in the tire receives the first RF signal, and when the pressure in the tire is greater than a predetermined pressure, the remote unit 14 transmits a second RF signal. Via the remote receiver 20, the controller 60 determines whether the second RF signal is received within a predetermined time after transmitting the first RF signal. When the second RF signal is not received within the predetermined time, the controller 60 assumes a pressure detection failure and causes a display to indicate this condition.

Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) has a layer (13) of ferroelectric material disposed on a semiconductor substrate (11) and a gate electrode (17) formed on a portion (26) of the layer (13) of ferroelectric material. The portion (26) of the layer (13) of ferroelectric material sandwiched between a semiconductor substrate (11) and a gate electrode (17) retains its ferroelectric activity. The portions (21, 22) of the layer (13) of ferroelectric material adjacent the portion (26) are damaged and thereby rendered ferroelectrically inactive. A source contact (31) and a drain contact (32) are formed through the damaged portions (21, 22) of the layer (13) of ferroelectric material.

Abstract: A portable electronic device (10) including a virtual image display (20) positioned within a housing (11) or a remote unit (30), capable of providing an image of information contained on a smart card (18) as well as transactions processed in response to data transmitted by a two-way voice transceiver (24) between a host database (118) and the portable electronic device (10). A sensor (19) constructed to have the smart card (18) positioned adjacent thereto in data sensing juxtaposition and electronics (22) connected to the sensor (19) for processing data between the host database (118) and the portable electronic device (10), and for reading and writing data to the smart card (18). The two-way voice communications transceiver (24) for transmitting and receiving data between the portable electronic device (10) and the host database (118), and the virtual image display (20) for supplying image data.

Abstract: A single input pin (48) provides multi-functional features for programming a power supply (10). By connecting the appropriate interface circuit (92, 100, or 112) to the single input pin (48), the power supply (10) is programmed for specific behaviors during power up and toggling of an on/off switch (96, 108). In one mode of operation a light emitting diode (106) in the interface circuit (100) is optically coupled to a microprocessor for signaling the closure of the on/off switch (108), allowing the microprocessor to control the power supply (10) through an opto-coupler (102). In another mode of operation, the single on/off switch (96) controls the power supply (10). In yet another mode of operation, Zener diode (118) in the interface circuit (112) controls the power supply (10) during brown-out and black-out conditions.

Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) has a layer (15) of ferroelectric material disposed on a semiconductor substrate (11) and a gate structure (27) formed on the semiconductor substrate (11). A source region (23) and a drain region (24) are formed on the semiconductor substrate such that the source region (23) and the drain region (24) are laterally spaced apart from the gate structure (27).

Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) is manufactured from a substrate (11) that has a layer (14) of ferroelectric material sandwiched between a substrate (13) and a layer (16) of silicon. A gate structure (24) is formed on the layer (16) of silicon. A source region is formed in a portion of the layer (16) of silicon adjacent one side of the gate structure (24) and a drain region is formed in a portion of the layer (16) of silicon adjacent an opposing side of the gate structure (24).

Abstract: A two stage operational amplifier circuit comprises a first stage (31) having an input (2, 4) and an output, and a second stage (33) having an input and an output (19). The second stage input is coupled to receive the first stage output. A feedback path (41, 45, 47, 51) is coupled between the output and the input of the second stage. The feedback path (41, 45, 47, 51) comprises a low-frequency compensation path (41, 45) and high-frequency compensation path (45, 47, 51). The feedback path (41, 45, 47, 51) is compensated such that the frequency response of the second output of the second stage is substantially 6 dB per octave throughout the high-frequency region.