Abstract: A control signalling arrangement for a pulse transmission system uses a main data stream including a block parity channel. Control signals are transmitted from an end terminal to a repeater by inserting the control signals in periodically spaced bit positions of the block parity channel. At the repeater, the control signals are separated from the block parity channel for controlling the circuits or devices for maintenance operations.

Abstract: A nonlinear optical device includes a layered semiconductor structure having layers of different energy band gap materials. Alternate layers of the structure are arranged for containing trapped charge. An input light beam is applied to the layers. A control light beam varies the trapped charge for controlling propagation of the input light beam through the structure.

Abstract: A converter circuit receives N-rail logic signals and converts them into a precision N-level signal. A pair of line drivers is connected in a balanced output arrangement with the primary winding of an output transformer. In response to the N-rail logic signals, weighted currents are conducted through an input impedance, connected with the line drivers, to a ground reference. As a result the line drivers conduct various levels and polarities of current through the entire primary winding of the output transformer. Thereby a precision N-level signal is produced in a secondary winding of the output transformer and at the converter output terminals.

Abstract: A digital latching circuit includes a quantizer having an input pair of emitter-coupled transistors connected with output transimpedance circuits. The quantizer is responsive to the state of an input signal applied to the input pair for producing from the output transimpedance circuits a quantized output signal. A feedback pair of emitter-coupled transistors is interposed between the outputs of the transimpedance circuits and the inputs to the transimpedance circuits. Current pulses are applied alternatively to the common emitter circuits of the input pair and the feedback pair of transistors for alternatively enabling the quantizing of the state of the input signal and the latching of that quantized state.

Abstract: A pipelined digital signal processor includes a common data and control bus (101) and a source (100,105) of instructions and data words. An arithmetic section (110) processes one data word with another data word through selected processing subsections performing operations according to an expression, thereby producing a resultant data word. A destination (105) receives the resultant data word from the arithmetic section. Control circuits (IR-L,M,N and IR-S,T) receive a single instruction (i.e., I.sub.i) during each processor cycle for controlling all processing subsections (112, 115, 116) operations. During each processor cycle, each processing subsection (i.e., 112) performs an operation relating to a different expression than the other processing subsections (i.e., 115 or 116) are performing during that processor cycle. All of the operations controlled by the single instruction (i.e., I.sub.i) are executed during a single processor cycle.

Abstract: A maintenance response signalling arrangement for a digital transmission system transmits response signals from a repeater to an end terminal. From the repeater, response information is modulated onto a subcarrier which is superimposed as a jitter signal on the main data stream. At the end terminal, the response information is recovered from the jitter signal on the main data stream.

Abstract: A decision circuit is responsive to digital input signals and to timing signals for reshaping and retiming the input signals into reshaped and retimed output signals. The decision circuit also is responsive to the digital input signals and absence of the timing signals for reshaping but not retiming the digital input signals into reshaped output signals which are transmitted. Thus the circuit produces and transmits reshaped output signals even upon failure to apply the timing signals required by a prior art decision circuit.

Abstract: A dual wavelength optical source includes a monolithic integrated pair of series-opposition connected diodes, each fabricated for emitting light having a different wavelength than the other. Polarity of a common bias current conducted through the diodes is reversed for activating alternatively light emission from the diodes. Active emission regions of the diodes are stacked upon one another for efficiently coupling the resulting beams of the different wavelengths of emitted light through a surface into the core of a single mode optical fiber.

Abstract: A method for fabricating an optical attenuator includes the following steps. Measuring the magnitude of optical loss imposed on an optical signal transmitted through first and second abutted optical fibers. Aligning the abutted ends of the first and second optical fibers for minimum distributed optical signal loss through both optical fibers, as measured at the far end of the second optical fiber. Heating the abutted ends of the first and second optical fibers into a plastic state. Physically distorting the optical fiber ends until the measured optical signal loss increases by a desired additional lumped optical loss value. Cooling the abutted ends of the first and second optical fibers to form a fusion splice imposing the desired additional lumped optical loss value between the ends of the first and second optical fibers.

Abstract: An advantageous method for fabricating an optical attenuator between the ends of two optical fibers uses the following steps. The axes of the cores of optical fiber ends are misaligned by an offset distance and then one of them is moved along its center axis until the ends of the fibers abut one another. Abutted ends of the optical fibers are melted. While the fiber ends are molten, surface tension aligns the axes of the cores of the optical fibers. Finally the abutted ends region of the optical fibers is cooled into a lumped optical attenuator.

Abstract: An optical device includes a layered semiconductor structure having a variable input light beam applied to the structure with an E field component polarized normal to the layers. Intensity of the input light beam controls charge trapped in the layers, the dielectric constant of the layers containing the trapped charge, and the propagation of the input light beam within the device.

Abstract: There is disclosed a method for fabricating an undersea communications cable core containing optical fibers. The method includes heating a central strength member and extruding a first layer of thermoplastic elastomer onto the heated central strength member. Paying out the optical fibers from a plurality of bobbins. Helically laying the optical fibers onto the first layer of thermoplastic elastomer with a planetary motion. The optical fibers passing entirely enclosed through a separate part of a whipping prevention enclosure from the bobbins to a rotating closing die. Passing the central strength member, coated with the first layer of thermoplastic elastomer and helically wrapped with the optical fibers, through the closing die, which rotates with the rotation of the helix, applying to the optical fibers forces directed radially into the core but without applying to the optical fibers forces directed tangentially to the surface of the first layer of thermoplastic material.

Abstract: A linear amplifier circuit includes input and output signal ports and a pair of signal amplifying circuits. Each signal amplifying circuit couples an input signal from the input signal port to the output signal port. A bias supply can be connected to the signal amplifying circuits for supplying bias currents thereto. The input and output signal ports are isolated from the bias supply without using capacitors or inductors.

Abstract: A pipelined digital processor includes a common data and control bus and a source (100 or 105) of instructions and data words. An arithmetic section (110) processes one data word with another data word through selected processing subsections (112, 115, 116) performing operations according to an expression, thereby producing a resultant data word and a status signal. A destination (105) receives the resultant data word from the arithmetic section. Control circuits (IR-C) decode a single conditional instruction for controlling performance of a specific condition test during a first subsequent processor cycle (i.e., i+2). The control circuits further decoding another instruction word during the first subsequent processor cycle for controlling all processing sections operations during a second subsequent processor cycle (i.e., i+3).

Abstract: There is disclosed an undersea communications cable containing optical fibers. The cable is fabricated so that fiber optical loss characteristics vary only slightly with changes in tensile strain in the cable.

Abstract: An undersea communication cable system repeater housing and electronic circuits mounting structure includes a vessel having an electrical insulator covering an inside surface of the vessel. A heat conducting structure for mounting electronic circuits includes separable segments having surface areas contoured to match an inside surface of the electrical insulator. Electronic circuits are mounted on the heat conducting structure. The separable segments of the heat conducting structure are inserted into the vessel as a unit with resilient devices interposed between the segments for pressing the contoured surface areas into intimate contact with the inside surface of the electrical insulator.

Abstract: A digital computer is arranged to process data through an arithmetic logic unit in response to instructions residing sequentially in an instruction register, each instruction requiring a single instruction interval for fetching data from a selected source in a store, processing the data in the arithmetic logic unit, and storing the result of processing the data into a selected destination in the store. Means are provided for moving a single bit from any selected one of a plurality of bit positions in the selected source to any selected bit position of a plurality of bit positions in the selected destination during a single instruction interval without affecting the state of any other bit of the selected destination.

Abstract: A cable termination arrangement includes a tapered socket body and a mating plug covered with a sleeve of malleable material. Cable strands are inserted and spread out inside of the socket. The plug and sleeve are pushed into the socket for forcing the strands into the sleeve. When a tensile force is applied to the cable, slippage between the cable and the socket is zero.

Abstract: A timing system, for distributing clock signals in a synchronous processing system having plural processing sections, includes a central clock circuit and a plurality of section clock circuits, each section clock circuit being located in and associated with a different one of the processing sections. Each section clock circuit is arranged to respond to a system clock signal for stepping through a plurality of states including a state common to the plurality of section clock circuits. An arrangement, responsive to the system clock signal, produces and transmits to the plurality of section clock circuits a synchronization signal that routinely sets the plurality of section clock circuits to the common state. The timing system may further include an arrangement for controlling suspension of processing in the plural processing sections.

Abstract: A control circuit for an injection laser includes a driver circuit which applies a driving current to the laser in response to an electrical modulating signal. A prebias circuit applies a prebias current to the laser in response to the difference between a signal derived from the electrical modulating signal and a signal derived from the laser light output.