Abstract: An optical pulse stream regenerator includes an optical receiver, a decision and timing circuit, and an optical transmitter. In response to an incident optical data pulse stream, a variable gain receiver section produces an electrical data pulse stream representing the incident optical data pulse stream. The receiver section is stabilized by having different variable gain devices respond to separate ranges of an automatic gain control signal. In response to the receiver section electrical data pulse stream, a phase-lock frequency-lock circuit in the timing circuit recovers a clock pulse stream that is synchronized with the incident optical data pulse stream, and the decision circuit regenerates an electrical data pulse stream representing the incident optical data pulse stream.

Abstract: A timing recovery circuit receives a timing component signal and generates a signal having a frequency varying in response to a control signal. In response to a difference between the phase of the variable frequency signal and the phase of the timing component signal, the circuit produces a control component. In response to cycle slips between the variable frequency signal and the timing component signal, the circuit produces a series of pulses having a polarity related to the sense of the cycle slips and having a pulse rate directly related to the rate of the cycle slips except when amplitude of the timing component signals falls below a predetermined value whereupon no pulses are produced. The control component and the series of pulses are combined into the control signal that adjusts the frequency of the generated signal into synchronization with the timing component signal.

Abstract: A precision crystal-controlled oscillator circuit with provision for separate sinusoidal and square-wave output signals which can be realized as a silicon integrated circuit without the use of external capacitors or resistors is disclosed. Two feedback loops are utilized in addition to the oscillating loop. The first feedback loop maintains the gain of the oscillation loop at substantially unity when the amplitude of the oscillation is at a predetermined level, thereby ensuring both spectral purity and amplitude stability of the sinusoidal output signal. The second feedback loop maintains the duty cycle of the square-wave output signal substantially equal to 50 percent by controlling the circuit operation to equally space the signal zero crossings at the input of the square-wave output stage.

Abstract: A sealed contact includes a capsule enclosing a pair of magnetic reeds. Each reed has a fixed end sealed in the capsule and a flat movable portion with side edges substantially parallel to one another for a predetermined length and tapered toward one another from the end of the predetermined length to the tip of the movable portion. The reeds are positioned so that the movable portions overlap one another by an overlap length and define an overlap area which is less sensitive to variation in overlap length than a conventional sealed contact having reeds cut substantially normal to the parallel side edges.

Abstract: A fluidic device comprising a housing having operate and release compartments separated by a passage is arranged with a pressure source for forcing a deformable moving element from either compartment into a deformation chamber connecting to the release compartment. The moving element is deformed to increase its potential energy by an amount which is sufficient to effect the element's movement from the deformation chamber to the operate compartment upon termination of the pressure.

Abstract: A cross-coupled flip-flop stage, or memory cell, for a word oriented array of memory cells is developed from four insulated-gate field-effect transistors which perform storage, loading, and gating functions of the cell. The functions of the cell are controlled by three different voltage levels coupled by a word line to all cells of a memory word.Associated with the array are bipolar transistor wordline-select and digit-write circuits used for achieving a low select-read-write cycle time for the memory cells.