Abstract: There is disclosed a method for fabricating an undersea communications cable containing optical fibers. The cable is fabricated so that fiber optical loss characteristics vary only slightly with changes in strain in the cable. During fabrication an adhesive bonds the cable core containing the optical fibers to a layer of steel wire for preventing creep therebetween.

Abstract: A monolithic integrated analog multiplier circuit includes a series aiding connection of semiconductor junctions, each junction being arranged for conducting an input current from one of plural sources of input currents and for producing a voltage proportional to a logarithm of the input current conducted therethrough. A pair of opposite conductivity type transistors have their base-emitter circuits arranged to respond to the voltages produced at opposite ends of the series aiding connection for converting the voltage produced across the connection into an output collector current proportional to the product of the input currents.

Abstract: A digital regenerator line includes in each station a status and error detection arrangement having an error detection circuit (64) responsive to a filtered composite output signal (101) from a low-pass filtered output from a digital regenerator (30) using quantized feedback. The filtered composite signal includes a stressing signal and a quantized feedback error burst. A high-pass filter (71) is responsive to the filtered composite signal for removing the stressing signal and for passing the quantized feedback error burst. First and second threshold comparators (72 and 76) responsive to the quantized feedback error burst produce a burst signal when the amplitude of the quantized feedback error burst crosses a predetermined threshold (V.sub.R1 or V.sub.R2). The occurrence of the burst signal is determined to indicate that an error has occurred in the output of the digital regenerator.

Abstract: A data control circuit (18) for an input/output arrangement is arranged for controlling the transfer of a data word through a shift register (20 or 120) to or from a peripheral device (22 or 122). The circuit (18) provides for selection between internal clock generation at one of several rates or application of an external clock and for selection of the length and format of the data words to be transferred. Selection is accomplished by an interval counter (38), format data stored in a control register (37), two gating circuits (30 and 40) and a selection circuit (35).

Abstract: A status reporting arrangement for a digital transmission system (10) has a plurality of stations (11, 12, 13) in a tandem configuration. Each station (such as 11) includes a reporting circuit (30) arranged for receiving (36) a train of messages (91, 96), each message originating from a different preceding station (such as 13 and 12) in the tandem configuration, followed by a received caboose signal (97). Each reporting circuit responds in turn to the train of messages and the received caboose signal by retransmitting (60) the train of messages (91, 96) but deletes the received caboose signal (97). The reporting circuit, in response to detection of the received caboose signal, appends to the retransmitted train of messages a message (100) from the local station and a new caboose signal (102).

Abstract: A microcomputer system arranged for performing direct memory access operations has direct memory access circuitry included on a single chip with the main processor of the microcomputer. Addressing for direct memory access operations is accomplished by circuitry also used for generating addresses when processing routine instructions in the main processor.

Abstract: A microcomputer having a 4-bit instruction register uses some double operation code (opcode) instructions thereby increasing its instruction set over the sixteen instruction limit imposed by the instruction register. During a single opcode instruction operation, a 4-bit opcode word is fetched from memory (20), is loaded into the instruction register (32), and is applied to a logic circuit (601, 603 or 621, 623). The resulting output from the logic circuit (601, 603 or 621, 623) determines the state of a latching device (610 or 630). The latching device (610 or 630) is latched into a first state in response to the output of the logic circuit, and the first opcode word stored in the instruction register controls processing of a data word to be fetched from storage. During a double opcode instruction operation, a first opcode word is fetched into the instruction register. The latching device (610 or 630) is latched into a second state in response to the output of the logic circuit.

Abstract: In a conditional transfer control circuit (10) for a controller (11) arranged for fetching instructions from a sequence of addresses wherein a list of instructions is stored, there is a circuit (25) for producing a first signal (C) representing a true or false condition resulting from executing an instruction in the list of instructions and a circuit (IRO) for producing applying a second signal (on lead 32 or 72) indicating whether control is determined by the first signal being true or by the first signal being false. An EXCLUSIVE NOR (or EXCLUSIVE OR) gate (30 or 70), responsive to the first and second signals, produces a condition transfer signal (on lead 18) that causes the controller to fetch a next subsequent instruction from an address other than the next subsequent address in the sequence of addresses wherein the list of instructions is stored.

Abstract: A sequential address generation arrangement (45, 61, 62, 99, 102) generates a sequence of addresses in response to an initial address and disables generation of the sequence of addresses in response to a control signal (LAST NIB) produced from at least a portion of the initial address at the conclusion of generation of a predetermined number of sequential addresses, the predetermined number being decoded from the initial address.

Abstract: An enhanced pole quality factor (Q) notch filter section circuit includes an active biquadratic notch filter section and a pole quality factor enhancement amplifier responsive to the output of the biquadratic notch filter section for providing at the input of the biquadratic notch filter section negative feedback in pass and stop bands of frequencies and positive feedback in the transition range of frequencies between the pass and stop bands of frequencies.

Abstract: An active variable equalizer is arranged to provide a Bode type variable equalizer characteristic without requiring an inductor. The equalization shape remains unchanged as the amount of equalization is varied. This equalizer uses a tandem arrangement of additive feedforward and negative feedback to achieve the mentioned equalization shape.A circuit interconnects with input and output terminals for combining input and output signals into an intermediate signal having a magnitude equal to a weighted sum of the input and output signals. A frequency dependent circuit responds to the intermediate signal for producing a frequency dependent signal that is combined with the input signal to generate the output signal.

Abstract: An active variable equalizer is arranged to provide a Bode type variable equalizer characteristic without requiring an inductor. The equalization shape remains unchanged as the amount of equalization is varied. This equalizer uses a tandem arrangement of additive feedforward and negative feedback to achieve the mentioned equalization shape.

Abstract: An access port, a basic building block for optical devices, is formed by joining the ends of two fibers. Each fiber has a wedge-shaped end portion with two planar sides. One planar side of one end portion is held against one planar side of the other end portion. The other planar side of each end portion controls transmission of light from the first fiber to the second fiber.Optical devices for monitoring, switching, attenuating or distributing the light transmitted through the first fiber advantageously use the access port.

Abstract: An integrated circuit digital-to-analog converter circuit of the binary weighted current summing type in which the emitter potentials of the transistor current sources are maintained substantially equal by controlling the voltage differential between the base electrodes of the current source transistors. In one disclosed embodiment, the base electrodes of the transistor current sources are connected to a resistive divider network and the voltage across each of the resistors is maintained substantially equal to (kT/q) ln 2. The disclosed circuit can be used as an alternative to, or in combination with, prior art emitter-scaling techniques.

Abstract: A roving reference automatic gain control (AGC) arrangement is used in a regenerator of a pulse code modulation (PCM) transmission system. An adjustable gain circuit receives a sequence of data pulses and produces a data-pattern-dependent input signal. A signal channel circuit, responsive to the input signal, produces a data-pattern-dependent detected signal. Regeneration circuitry, responsive to the input signal, produces a regenerated data-pattern-dependent output signal. A reference channel circuit, responsive to the output signal, produces a data-pattern-dependent reference signal. A circuit algebraically combines the detected signal with the reference signal to form a continuously-variable data-pattern-independent gain control signal which is applied to the adjustable gain circuit for controlling the gain thereof.

Abstract: The speech synthesizer minimizes storage requirements by storing basis functions each defining a waveform segment or phoneme within a pitch period and including formants F1 and F2, featuring readin at one rate and readout at different rates within the pitch period. The synthesizer is characterized by each basis function being represented by a data point plotted on a single line on a chart having first and second formant log-log axes and means for producing a speech waveform segment approximately representing any desired point located off of the single line on the chart by selecting and reading out of the memory one of the basis functions at a rate different than the basic storage rate.

Abstract: A single amplifier is arranged in an immittance network for simulating a pure frequency dependent negative resistor (FDNR).

Abstract: A selective calling circuit includes a central control code generator for generating a digital stream having repetitions of selected code words of digital information for selectively calling a plurality of remote receiving stations in this circuit. Each remote station includes a decoder for recognizing a predetermined sequence of digital information and reconstructing selected digital code words included therein.A variable modulus counter, responsive to clock pulses and means for selectively varying the modulus of the counter, is included in the code generator at the central control station.A resettable counter that counts in response to clock pulses and is reset in response to received code signals is included in the decoder at the remote station.

Abstract: A family of window comparator circuits are arranged to monitor differential input signals and indicate when the difference between the signals is between two limits. Each of the window comparator circuits includes an input circuit having at least one current source. The input circuit is responsive to a differential input signal for conducting two dependently variable currents through an output circuit. At least one voltage dropping element is connected to each current source in the input circuit for establishing the limits of the window comparator. The output circuit responds to changes in the ratio between the two currents conducted therethrough for indicating that the differential input signal is between the two limits.

Abstract: A narrow-band tone decoder has a controllable oscillator, connected in a fast-capture phase-locked loop, for generating a signal having a frequency determined by a control signal produced within the loop. A synchronous detector, which responds to an input signal of the tone decoder and to a signal from the controllable oscillator, produces a signal having a magnitude dependent upon the magnitudes of the input signal and of the signal from the controllable oscillator. A window comparator monitors the control signal within the loop for deciding when the generated signal is within a predetermined frequency range.