Abstract: A ping-pong data buffer mechanism for transferring data from one data bus to another data bus is described. This mechanism includes a dual port storage mechanism having a single storage array and two independent ports with each port having its own separate data, address and control lines. Write circuitry is coupled to one of the independent ports for receiving data from one of the data buses and storing it into a first portion of the storage array. Read circuitry is coupled to the other of the independent ports for simultaneously reading data from a second portion of the storage array and supplying it to the other data bus. Mode control logic is provided for enabling the storing and reading functions of the first and second portions of the storage array to be interchanged back and forth from time to time so that data may be read from one portion while data is being stored into the other portion and vice versa.

Abstract: A method of operating a timer mechanism in a digital data processing system is described in which the contents of at least one timer register is updated by a predetermined time increment during each of successive periodic update cycles. Each update cycle includes a predetermined number of operating cycles of the data processing system. During each update cycle, the contents of an adjustment register is circularly shifted by one bit position and if the bit value at a particular position in this adjustment register has a predetermined binary value during an update cycle, then actual updating of the timer register is omitted during a related update cycle.

Abstract: A reconfigurable automatic tasking system. A host system is capable of executing interactively initiated operations or tasks. A device is provided for executing a program having an interfacing program loaded therein. The interfacing program is adapted to define and to execute a task repeatedly. An interface is connected to the host system and to the device for executing a program that issues commands to and receives data from the host. An independent program is connected to the task that is defined by the interfacing program. This independent program adds generality to the interfacing program after the task has been defined.

Abstract: A bus-to-bus adapter is provided for coupling the input/output bus of a first data processor to the input/output bus of a second and different type of data processor. The adapter enables the transfer of data and messages from the first processor to the second processor and vice versa. The adapter includes a buffer storage unit and control logic for enabling multiple data buffers to be provided for enabling multiple independent data transfer operations to be performed in a concurrent manner. The control logic also includes a mechanism for allowing the reading out of data from a data buffer to begin before such data buffer has received all of its incoming data. The adapter further includes a programmable service time allocation mechanism for limiting message service time relative to data transfer service time and for providing different amounts of data transfer service time for different ones of the multiple data buffers.

Abstract: A system for testing certain attributes (i.e., performance and usability) of an interactive system program. A memory device stores data representative of interactive commands generated by a user. A device is also provided for executing an emulator overlay connected to the memory device for receiving data therefrom and modifying it in subsequent transmission. The emulator overlay has a time measuring device associated with it for determining performance of an interactive system program. A device is also provided for storing and executing an interactive system program connected to the emulator overlay. Finally, another memory device is provided for storing the data representative of system program performance.

Abstract: A microprocessor chip which is capable of executing a specific subset of instructions on behalf of the main storage portion of a computer memory can be made to emulate direct execution instructions not in that specific subset while working on behalf a control storage portion of the computer memory in a manner which is transparent to the main storage portion by means of a novel set of operand space selection instructions in the control storage portion and a novel switching circuit on the microprocessor chip which controls the access of the chip to the control store portion and the main store portion.

Abstract: At least-recently used (LRU) storage means and its associated logic maintain usage history for associativity class entries of a cache directory. The storage means includes an independent storage array for each of the bit positions of an LRU binary code pattern. Parity bits are provided in the arrays for each LRU bit. Separate read/write controls simultaneously write updated LRU bits to some of the arrays and read out unchanged LRU bits from the remaining arrays during updating of a usage history entry when its associativity class is used. Pattern checking logic collects the update bits and the unchanged bits during the update cycle to determine whether or not the new entry is a valid LRU combination. A parity bit is written with each of the update LRU bits written into the arrays and parity bits are read out from the arrays with the unchanged LRU bits for parity checking of each unchanged LRU bit during updating of usage history entries.

Abstract: A system for designing an intercommunication network among a plurality of devices. The system includes a device for storing rules to meet design requirements and a mechanism connected to the device for storing rules in order to revise the rules dynamically. Also provided is a device for storing data and a mechanism connected to the device for storing data in order to revise the data. A requestor has the ability to access all rules and to revise a portion of the data. Moreover, a designer has the ability to access all rules and to revise another portion of the data, which portion has at least one subportion that cannot be revised by the requestor.

Abstract: A system for producing human readable physical data in text form from geometric data in mathematical form that partially describes a three dimensional object. A first database is provided that contains geometric data in mathematical form representative of the shape of the object. A second database contains physical data in text form. At least a portion of the data in the first database can be extracted and used as the basis for calculations of physical data in mathematical form, which can be converted into human readable physical data in text form. The resulting physical data can be merged with data from the second database to produce a complete geometric description in text of the object. The present invention also contemplates a mechanism for using empirical data with a knowledge based system. The knowledge based system can be used to modify the physical data to adapt geometric properties to a manufacturing process.

Abstract: A non-saturating voltage output driver circuit. A controlling mechanism is connected to a current source, a reference voltage and a load. A pre-driver is also connected to the current source. Connected to the controlling mechanism, the pre-driver and the load is a down-level output driver, the output of which is dependent on the reference voltage, but kept out of saturation and substantially constant over a temperature range.

Abstract: A system for automatically selecting part numbers and for loading data, which guarantees compatibility of a plurality of devices. A database maintainable by a user is provided to store part numbers and descriptions thereof. A mechanism is provided for selecting an item from the database based on a description and data in the database. Another mechanism is provided for selecting another item from the database as a function of its description, of the first item and of data relating the respective descriptions of both items to one another. Another mechanism is provided for successively selecting items from the database as a function of descriptions, of previously selected items and of data relating descriptions of at least some of the items to descriptions of other items.

Abstract: A full bridge non-resonant switching circuit is disclosed which has an inductive device and four switches. Parasitic controlling mechanisms are operatively connected to the four switches to control inductive energy release in order to switch current through the switches at substantially zero voltage.

Abstract: The present invention is directed to a relational data base system which is operating in a virtual machine environment. The invention provides a system that includes a disconnected virtual machine which is running in the same virtual machine environment as is the relational data base. Insert and Update requests to the system are generated by programs running in user controlled virtual machines. Other users issue select and view requests which lock out insert and update requests which relate to the same data domain. With the present invention Insert and Update requests go to the disconnected virtual machine which ques them and applies them against the relational data base in the order that the requests are received. In this way, while a select is being executed on data in a particular domain of the data base, update and insert request for the same domain will be held by the virtual machine and the operator will not be "locked out" of the system.

Abstract: A method of operating a digital data processor includes the supplying to the digital data processor of a branch and return on address (BAROA) instruction having an operation code field, a memory entry address field and a memory exit address field. This method also includes for such branch and return on address instruction the steps of loading the operation code field into an instruction register, loading the memory exit address field into an address register and loading the memory entry address field into a program counter. This method further includes storing the next sequential address following the address of the current BAROA instruction into a register stack, and then fetching from memory and executing a sequence of instructions starting with the instruction residing at the memory entry address provided by the branch and return on address instruction. The program counter is incremented each time an instruction is executed.

Abstract: A microword generation mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword generation mechanism includes a first programmable logic array mechanism responsive to the processor instruction to be executed for providing the first microword needed in the execution of such instruction. This microword generation mechanism also includes a second programmable logic array mechanism responsive to the processor instruction to be executed for providing the second microword needed in the execution of such instruction. This microword generation mechanism further includes at least one additional programmable logic array mechanism responsive to the processor instruction to be executed for providing the remainder of the microwords needed to execute such instruction.