Abstract: Apparatus and method for decoding computer operation codes. The operation code is decoded into a single product term in the AND array of a programmable logic array. That single product term is then processed through a clock driven sequencer to generate a plurality of sequential product terms. These sequential product terms are decoded by the OR array of the programmable logic array to generate a plurality of sequential time states comprising the decoded operation code.

Abstract: An improved flexible leader for use in conveying ink ribbon from a ribbon box to the print point of a printer or typewriter is disclosed. The leader is a U-shaped channel with top latches which protects the ribbon from operator contact and provides good ribbon tracking. Vertical raised ridges on the insides of the channel reduce frictional contact between the ribbon and the leader. The leader is easy to install.

Abstract: A microword control system is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword control system includes a plurality of programmable logic array mechanisms responsive to the processor instruction to be executed for individually producing different ones of the microwords needed to execute such instruction. This microword control system also includes microword-responsive control circuitry for controlling the operation of the data processor. This microword control system further includes multiplexing circuitry for supplying microwords from different ones of the programmable logic array mechanisms to the control circuitry during different time intervals.

Abstract: An integrated circuit mechanism is provided for coupling the separate sets of output lines from a plurality of programmable logic arrays to the same set of bus lines of plural-line signal transfer bus. This coupling mechanism includes precharge circuitry for precharging each of the bus lines during a first time interval. This coupling mechanism also includes a separate strobe signal line for each programmable logic array and circuitry for activating one of the strobe signal lines during a second time interval for selecting a particular programmable logic array. This coupling mechanism further includes a separate output buffer for each programmable logic array. Each such output buffer includes a plurality of buffer stages for individually coupling the different ones of the programmable logic array output lines to their respective bus lines.

Abstract: A clocking mechanism is provided for multiple overlapped dynamic programmable logic arrays which are used in a digital control unit wherein a sequence of control words are used to produce successive groups of control point signals. Such a control unit includes a plurality of dynamic programmable logic arrays for individually producing different ones of the control words. Each such control word includes a strobe field which is coded to identify a programmable logic array other than the one which produced it. The control unit also includes control circuitry responsive to the control words for producing the control point signals for successive machine control cycles. The control circuitry includes circuitry responsive to the strobe field in each control word for producing a strobe signal for selecting the next programmable logic array to supply a control word to the control circuitry.

Abstract: A digital data signal transfer mechanism is provided for use in large scale integration digital data processor circuitry formed on an integrated circuit chip. The signal transfer mechanism includes a plural-bit data bus formed on the integrated circuit chip for transferring plural-bit binary data signals between different locations on the chip. The signal transfer mechanism also includes plural-bit signal source circuitry and plural-bit signal destination circuitry formed on the integrated circuit chip and coupled to the plural-bit data bus for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus.

Abstract: A microcode control mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed data processor. This microcode control mechanism includes sequence counter circuitry for supplying a sequence of numbers and a programmable logic array mechanism responsive to the processor instruction and to the sequence of numbers for producing a sequence of microwords needed to execute the instruction. The microcode control mechanism also includes repeat circuitry responsive to a predetermined microword produced by the programmable logic array mechanism for setting the sequence counter circuitry back to a count which is less than the current count for causing a selected portion of the microword sequence to be repeated. The microcode control mechanism further includes a programmable repeat counter for counting the number of times the selected portion is repeated and for disabling the repeating action after a selected number of repeats.

Abstract: A tristate driver circuit is provided on an integrated circuit chip for driving a bus line or signal line located off of the chip. This circuit very rapidly charges the bus line or signal line to positive voltage level each time and just before it switches to its tristate or high impedance output condition. This eliminates the need for a pull-up resistor or pull-up transistor to be connected to the off-chip bus line or signal line.

Abstract: Rather than repeatedly using the entire length of a multi-color print ribbon in an impact printer until the reaching of a lower quality threshold requires replacement of the ribbon, this invention causes only a subsection of limited length of the ribbon to be used until the lower quality threshold of any one of the color tracks of this subsection is reached, after which the ribbon is advanced to enable use of a fresh subsection.The quality status of the currently used subsection may be monitored by counting the number of impacts on each individual color track and comparing that number with a predetermined, stored value, or by shining light through the ribbon and optically comparing the passing light with a preset value. The method is flexible enough to permit manual advance of the ribbon to a fresh subsection in case a printing job requires highest possible quality.

Abstract: There is disclosed apparatus and a method for extending a parallel channel of the host processor over a serial link to a remote peripheral device. The apparatus includes a microprocessor within I/O channel extension logic which responds to either instructions or data from a host processor. The instructions are of the type commanding the I/O device to perform a specific operation and the data is provided in response to requests for data from the I/O device. The channel extension logic is coupled to the host processor's channel and thus is able to obtain data from the host storage by cycle steal techniques. Within the channel extension logic are means to serialize the information and transmit it in a serial manner over the link. The microprocessor within the channel extension logic creates a frame, including a control byte, which identifies the type of information followed by the data, which frame is then communicated over the serial link to the I/O device.

Abstract: A microword control mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed data processor. This microword control mechanism includes circuitry (15, 20) responsive to a processor instruction to be executed for providing an instruction dependent signal uniquely representative of such instruction. This microword control mechanism also includes sequence counter circuitry (18) for supplying a sequence of number signals. This microword control mechanism further includes a programmable logic array (17) responsive to the instruction dependent signal and to the sequence of number signals for producing a sequence of microwords needed to execute the processor instruction.

Abstract: Binary logic structure is described which requires less space on an integrated circuit chip. This structure includes an encode programmable logic array responsive to a first group of binary input signals for producing a smaller number of binary signals which are encoded to identify different binary value combinations for the first group of binary input signals. This structure further includes a decode programmable logic array responsive to a second group of binary input signals and to the encoded binary signals produced by the encode programmable logic array for producing binary output signals representing logical functions of binary input signals in both the first and second groups. The chip space occupied by the encode programmable logic array is less than the additional chip space that would be required if the encode and decode programmable logic arrays were replaced by a single programmable logic array for receiving all the binary input signals in both the first and second groups.

Abstract: Improved tristate control circuitry is provided for a driver circuit formed on an integrated circuit chip. A parallel-connected combination of a depletion mode transistor and an enhancement mode transistor is connected in series in the voltage supply path for the driver circuit for controlling whether the driver circuit is in an active mode or a standby mode by controlling the supplying of operating voltage thereto. A further enhancement mode transistor provides a shunting action between the driver circuit side of the parallel-connected transistors and circuit ground to further aid in the control of the driver circuit operating mode.

Abstract: A cycle steal mechanism for enabling a host processor to initiate and control the cycle stealing of data to or from a storage unit located in an I/O controller which is connected to the I/O channel bus of the host processor. The I/O controller also includes a microprocessor and a direct memory access (DMA) unit either or both of which can be used to control the transfer of data between the I/O controller storage unit and the host processor. Typically, the DMA unit is used for cycle stealing data between the controller storage unit and the host processor. The cycle steal mechanism of the present invention enables the host processor to also initiate and control the cycle stealing of data to or from the controller storage unit without interrupting the program running in the controller microprocessor and without interrupting the cycle stealing operations of the DMA unit.

Abstract: A cycle steal mechanism for enabling a host processor to initiate and control the cycle stealing of data to or from a storage unit located in an I/O controller which is connected to the I/O channel bus of the host processor. The I/O controller also includes a microprocessor and a direct memory access (DMA) unit either or both of which can be used to control the transfer of data between the I/O controller storage unit and the host processor. Typically, the DMA unit is used for cycle stealing data between the controller storage unit and the host processor. The cycle steal mechanism of the present invention enables the host processor to also initiate and control the cycle stealing of data to or from the controller storage unit without interrupting the program running in the controller microprocessor and without interrupting the cycle stealing operations of the DMA unit.

Abstract: An I/O controller for transferring data between a host processor and one or more I/O devices. This I/O controller includes a microprocessor, a direct memory access controller and a dual port storage unit, one port of which is coupled to the host processor I/O channel bus and the other port of which is coupled to the microprocessor bus. All data transfers are by way of the dual port storage unit. The I/O controller includes an interleaving mechanism for enabling concurrent performance of two different modes of data transfer between the host processor and the I/O controller. In particular, this interleaving mechanism enables host processor direct program control (DPC) data transfers to be performed at the same time that the I/O controller is busy doing cycle steal data transfers for a block of data. These DPC data transfers are accomplished without interrupting the cycle stealing operations.

Abstract: A programmable sequential logic array mechanism is provided for performing logical operations and solving logical equations. The mechanism includes a search array subsystem for receiving a plurality of binary input signals. The search array subsystem includes an addressable storage array for supplying input control words for testing for different input signal conditions. The sequential logic array mechanism also includes a read array subsystem for producing a plurality of binary output signals. This read array subsystem includes an addressable storage array for supplying output signal control words. The results of the tests performed by the search array subsystem are used to select which ones of the output signal control words are allowed to establish or change the read array output signals.

Abstract: Serial storage interface apparatus for coupling a serial storage mechanism, such as a charge coupled storage device or a magnetic bubble storage device, to a data processor input/output (I/O) bus. Speed control circuitry is provided for causing the serial storage mechanism to operate at a higher speed when the data processor is responding more rapidly to data transfer requests from the interface apparatus and at a lower speed when the data processor is responding less rapidly to data transfer requests from the interface apparatus. This speed adjustment feature reduces the amount of data buffering required for interfacing a serial storage mechanism to an asynchronous variable response time I/O bus system.