Abstract: A data interface mechanism for interfacing bit-parallel data buses of different bit widths. This mechanism provides an automatic and efficient mechanism for converting data bytes into plural-byte data words and vice versa. The mechanism utilizes a plurality of random access (RAM) storage units located between the two data buses and an addressing structure wherein the higher order address bits are supplied to a chip select decoder to produce different chip select signals which are used to select different ones of the RAM units. For successive data transfers to or from the narrower data bus, storage addresses are used which produce different chip select signals which select the different RAM units one after the other in a sequence which repeats itself. Thus, successive data bytes to (from) the narrower bus are transferred from (to) the different RAM units in a rotating manner.

Abstract: A storage address link register system for enabling nested program branching wherein a first subroutine may call a second subroutine which is executed before the first subroutine returns program control back to the program which called it. The system includes a mechanism whereby the same set of storage address link registers may be used for nested branching both during the execution of a normal program and during the execution of an interrupt service program which breaks into the normal program and takes over control of the processor for a short interval of time. A mechanism is provided for saving the normal program values in the link registers at the commencement of the interrupt service program. A further mechanism is provided for monitoring the usage of the link registers by the interrupt program for enabling the normal program values to be restored in the link registers only after all interrupt program values have been removed from such link registers.

Abstract: A data processor input/output controller which is particularly useful as a microcontroller for the transfer of data between a host processor and one or more peripheral input/output devices in a digital data processing system. This input/output (I/O) controller is a subchannel controller for offloading a goodly portion of the subchannel control function from the host processor. This I/O controller includes a microprocessor for assisting and supervising the controller internal operations. Also included in the controller is an automatic high-speed data bypass mechanism whereby data may be transferred from the host processor to the I/O device or vice versa without having to pass through the microprocessor and without requiring any intervention on the part of the microprocessor during such automatic transfer.

Abstract: A micro processor controlled user programmable communications multiplexer subsystem (herein referred to by the symbol PCS) capable of transmitting and receiving data on any one or more of 32 communications lines simultaneously. Each line may be dynamically assigned to a variety of communication characteristics, such as line speeds, character lengths, synchronous, or asynchronous operation, and code structures as well as protocol selections.The system of the invention provides the capability for the user to write his communications programs using novel operations commands that provide code structure and protocol independence as well as communication line independence. Various hardware features and queuing techniques are employed in order to maintain high transmission rates.Variable line scanning in the Teleprocessing Time Division Multiplexer of the PCS is programmably permissible; i.e.

Abstract: A programmable control latch mechanism which is particularly useful in a microprocessor. One or more control latches are provided which can be set or reset under direct program control directly from the instruction register of a data processor by the loading therein of a unique program instruction. The unique instruction includes for each control latch two predetermined bit positions, one of which determines whether or not the control latch is to be changed and the other of which determines the binary value to which the control latch is to be changed. This enables anywhere from one to all of the control latches to be changed by a single instruction and enables each latch which is changed to be changed to any desired binary value. The control latch outputs can be used for storage page selection, direct control of external devices or circuits, selection of internal processor functions and the like.

Abstract: A priority level controlled unit for use in a microprogrammed digital data processing system for handling interrupt requests from interrupt sources having different interrupt priority levels. Each interrupt request is a plural-bit request having a priority level field and an interrupt source identifying field. A plural stage shift register is provided, each stage having enough bit positions to hold a single interrupt request. Successive shift register stages are assigned to successively lower priority levels. The interrupt requests are supplied one at a time to the highest priority level stage in the shift register. A separate comparator mechanism, coupled to each shift register stage, compares the priority level field of an interrupt request residing therein with the priority level value assigned to such stage for indicating priority level matches and mismatches. If a priority level mismatch is indicated for any given stage, then the interrupt request therein is transferred to the next shift register stage.

Abstract: A high performance channel-to-channel adapter for interconnecting two or more digital computers or digital data processors. Multiple input/output device addresses are recognized by the channel-to-channel adapter. The channel-to-channel adapter makes the proper processor-to-processor connection by matching device addresses. In particular, it interconnects for data transfer purposes the two processors for which the same device address has been received. The assignment of device addresses for processor use and the direction of data transfer are by conventions agreed to among the software systems executing on the interconnected processors. The channel-to-channel adapter does not have a view of these conventions. In the more general case, two device addresses are assigned by software convention to each processor-to-processor link, one address being used to transfer data in one direction and the other address being used to transfer data in the opposite direction.

Abstract: Data format converting apparatus is described for simultaneously converting multiple bytes of zoned decimal data to packed decimal data or vice versa. In the preferred embodiment, this format converting apparatus is obtained by adding a minimum amount of additional circuitry to a multibyte flow-through type data shifter used for providing the normal data shifting operations in a digital data processor. In particular, a zoned-decimal-to-packed-decimal conversion capability is provided by combining additional switching logic with the normal shifter switching logic for enabling the conductors for nonadjacent data fields on the shifter input data bus to be coupled to the conductors for adjacent data fields on the shifter output data bus. A packed-decimal-to-zoned-decimal conversion capability is provided by adding further switching logic for enabling the conductors for adjacent data fields on the shifter input data bus to be coupled to the conductors for nonadjacent data fields on the shifter output data bus.

Abstract: Channel data buffer apparatus for buffering data being transferred between an input/output channel unit and a main storage unit in a digital data processing system. In the disclosed embodiment, data is generally transferred between the channel unit and the data buffer (a "channel/buffer" transfer) in two-byte segments and between the main storage unit and the data buffer (a "storage/buffer" transfer) in eight-byte segments. The data buffer is comprised of eight column-forming byte-wide multirow storage arrays each having its own address mechanism for accessing any desired row therein. Corresponding rows in the different storage arrays provide the corresponding eight-byte rows for the data buffer as a whole.

Abstract: An instruction execution modification mechanism is described for a digital data processor wherein multiple programs or tasks are performed in a concurrent manner by means of a time slice mechanism which causes the instructions from the different programs to be executed in an interleaved manner. Instructions from the different programs are executed during different successive time slice intervals. The instruction execution modification mechanism is responsive to the occurrences of various predetermined conditions in the data processing system for selectively modifying the normal execution of different ones of the instructions in different ones of the programs. To this end, there is provided a program list mechanism listing the modifiable programs, an instruction list mechanism listing the modifiable instructions and a modification storage mechanism for storing modification signals for the different instructions.

Abstract: An instruction retry mechanism for enabling a digital data processing system having main, buffer and local stores to restart and, in most cases, recover from an error or failure in the processor hardware associated with the buffer and local stores. A first copy storage mechanism is provided for temporarily storing copies of data written into the local store. Two separately addressable multibit copy storage locations are provided for each local store address. One is capable of holding a copy of the latest data written into a given local store address during the most recent machine instruction cycle involving such address, and the other is capable of holding a copy of the latest data written into the same local store address during the next most recent machine instruction cycle involving such address.A second copy storage mechanism is provided for temporarily storing copies of data written into the buffer store by the instruction processing or instruction execution portion of the system.

Abstract: A laser beam is applied to a workpiece by means of a spring-loaded metal nozzle which engages the workpiece. An aperture in the workpiece end of the nozzle accurately defines the size of the hole formed in the workpiece by the laser beam. A chamber located within the lower end of the nozzle is continuously evacuated by a vacuum pump to remove the drilling debris. Adjustment of the degree of vacuum within the nozzle adjusts the bearing pressure of the nozzle on the workpiece.

Abstract: Size exception detection hardware for use with a digital data processor arithmetic unit for providing high-speed detection of lost data which results from storing an arithmetic result in a destination which is smaller than one or both of the source operands. In response to data processing machine instructions, the arithmetic unit performs arithmetic operations on variable length operands and sends the arithmetic results to variable length destinations. The operand and destination lengths are specified by length fields in the machine instruction. The destination length is specified independently of at least one of the operand lengths and hence may be less than such operand length. The size exception detection hardware looks at both the output field of the arithmetic unit and the destination length field in the machine instruction and generates a size exception program interrupt signal when the part of the arithmetic unit output field located outside of the destination length contains significant data.

Abstract: A digital arithmetic unit for adding and subtracting multidigit binary coded decimal numbers having a zoned format. Such adding and subtracting is done by means of a parallel binary adder of a type suitable for handling pure binary numbers and having no special provisions for accommodating zoned decimal numbers. The two multidigit zoned decimal numbers to be added or subtracted at any given moment are supplied to the two input sides of such binary adder by way of input modifier circuits which precondition the zone and sign fields in such numbers to enable the proper propagation of digit carries across such zone and sign fields during the performance of the addition inside the binary adder. The resulting binary bit sequence appearing at the output side of the binary adder is passed to an output modifier or corrector which causes the bits in the zone and sign field positions therein to assume the proper zone and sign code values.

Abstract: Data processing circuitry for performing two serially related arithmetic operations during one and the same machine control cycle and employing an independent zone parallel type arithmetic unit capable of simultaneously performing independent arithmetic operations in the different zones thereof. Data transfer circuitry is provided for immediately supplying the output result of a first arithmetic unit zone back to the input of a second arithmetic unit zone for immediately producing a second and different result. Such transfer circuitry is constructed to operate in an asynchronous manner so that the first result is supplied back to the input of the second arithmetic unit zone as soon as it becomes available at the output of the first arithmetic zone. Thus, a second result, which is dependent on the first result, is produced during the same machine control cycle as the first result. This data processing circuitry is particularly useful for providing storage protection for a data processor.

Abstract: A carry look-ahead parallel digital adder having a relatively wide overall data flow width and a pair of automatically adjustable boundary mechanisms for subdividing the adder into plural independent operating zones of variable width and variable location. Anywhere from one to three independent zones may be obtained. Independent external carry-in and carry-out lines are provided for each zone and the connecting points for such lines are automatically shifted in step with the movement of the zone boundaries.

Abstract: A digital arithmetic unit employing a binary adder for adding and subtracting multidigit binary coded decimal numbers in either zoned format or packed format and having an improved method of generating parity check bits for the resultant data bytes produced by the arithmetic unit. When using a binary adder for adding or subtracting binary coded decimal numbers, it is necessary to correct some of the data appearing at the output of the binary adder in order to obtain the correct results. The parity check bit generating circuitry of the present invention, however, works on the uncorrected data appearing at the output of the adder, but nevertheless produces the proper parity check bits for the corrected data which represents the final output for the arithmetic unit. This reduces the amount of time delay which would otherwise be caused by generating the parity check bits in a conventional manner.