Abstract: An apparatus and method are provided for accelerating the evaluated output of an P-domino latch. The apparatus includes evaluation P-logic, latching logic, keeper logic, and acceleration logic. The evaluation P-logic is coupled to a first N-channel device at a pre-charged node, and is configured to evaluate a logic function based on at least one input data signal. The latching logic is coupled and responsive to a clock signal and the pre-charged node. The latching logic controls the state of a latch node based on the state of the pre-charged node during an evaluation period between a first edge of said clock signal and a second edge of the clock signal. The latching logic otherwise presents a tri-state condition to the latch node. The keeper logic is coupled to the latch node. The keeper logic maintains the state of the latch node when the tri-state condition is presented, and provides a complementary state of the latch node at a complementary latch node.

Abstract: In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.

Abstract: For routing packets by rules in a packet network, a system and method in a routing device for selecting rules to apply to packets having each N fields in a header, considers rules as entities in N-dimensional space, projects the rules onto N-axes in the space, marks the beginning and ending of each projection as breakpoints, numbers intervals between breakpoints in sequential binary numbers, associates a subset of the set of rules as applicable to each interval between breakpoints on each axis, then considers a packet as a point in the N-dimensional space according to its header field values, locates the binary numbered interval into which the point projects on each axis by performing a search on each axis for the numbered interval into which the point projects on that axis, thereby determining the subset of rules applying to the packet for that axis, and determines the second set of matching rules from the subsets of rules by selecting those rules as matching the packet that apply to the packet on at least o

Abstract: A method and apparatus are provided for processing repeat string instructions with increased efficiency in a processor pipeline. Rather than explicitly generating an initial count register setup micro instruction each time a repeat (REP) prefix in encountered, the processor includes a shadow ECX register operating in parallel with an architectural ECX count register. This enables the contents of the architectural ECX register, which are also stored in the shadow ECX register, to be immediately transferred to an internal count register from the shadow ECX register upon the first iteration of a repeat string micro code sequence.

Abstract: An apparatus and method are provided for accelerating the evaluated output of an N-domino latch. The apparatus includes evaluation N-logic, latching logic, keeper logic, and acceleration logic. The evaluation N-logic is coupled to a first P-channel device at a pre-charged node, and is configured to evaluate a logic function based on at least one input data signal. The latching logic is coupled and responsive to a clock signal and the pre-charged node. The latching logic controls the state of a latch node based on the state of the pre-charged node during an-evaluation period between a first edge of said clock signal and a second edge of the clock signal. The latching logic otherwise presents a tri-state condition to the latch node. The keeper logic is coupled to the latch node. The keeper logic maintains the state of the latch node when the tri-state condition is presented, and provides a complementary state of the latch node at a complementary latch node.

Abstract: A microprocessor apparatus is provided that enables write back and invalidation of a block of cache lines from memory. The apparatus includes translation logic and execution logic. The translation logic translates a block write back and invalidate instruction into a micro instruction sequence that directs a microprocessor to write back and invalidate a block of cache lines from cache to memory, where the number of cache lines in the block has been previously entered in a register in the microprocessor by a preceding micro instruction. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that writes back data corresponding to each of the cache lines within the block.

Abstract: An apparatus and method are provided to support the provision of context-sensitive help functions in a back-end HTML/XML server. The apparatus provides partner-sensitive help functions to users that have been redirected from a plurality of partner sites to the back-end server. The apparatus has a data base and a context-sensitive help engine. The data base stores general help data, as well as partner-specific metadata corresponding to the plurality of partner sites. The context-sensitive help engine is coupled to the data base. The context-sensitive help engine receives a help transaction request that has been redirected from a specific one of the plurality of partner sites. The context-sensitive help engine provides specific help functions in response to the help transaction request, where the specific help functions correspond to the specific partner site.

Abstract: A microprocessor apparatus is provided for performing a pop-compare operation. The microprocessor apparatus includes paired operation translation logic, load logic, and execution logic. The paired operation translation logic receives a macro instruction that prescribes the pop-compare operation, and generates a pop-compare micro instruction. The pop-compare micro instruction directs pipeline stages in a microprocessor to perform the pop-compare operation. The load logic is coupled to the paired operation translation logic. The load logic receives the pop-compare micro instruction, and retrieves a first operand from an address in memory, where the address is specified by contents of a register. The register is prescribed by the pop-compare micro instruction. The execution logic is coupled to the load logic. The execution logic receives the first operand, and compares the first operand to a second operand.

Abstract: An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus includes a first table, a second table, and selection logic. The first table stores branch histories for a first set of branch instructions where the first set, when executed, exhibits a bias toward a first outcome. The second table stores second branch histories for a second set of branch instructions, where, the second set, when executed, exhibits a bias toward a second outcome. The selection logic is coupled to the first and second tables. The selection logic selects a particular branch history from either of the first or second tables. Thus, a branch prediction is made based upon contents of a branch history that is selected from a table containing branch histories for other branch instructions that exhibit the same outcome tendency as the particular branch instruction, thereby reducing the negative effects of aliasing.

Abstract: A timing debug tool for an IC that enables varying the skew of selected edges of a primary clock signal for a controllable number of clock cycles. The debug tool enables identification, isolation and analysis of timing problems on the IC. An IC including programmable clock skew logic that applies a programmed skew amount to selected edges of a clock signal. A debug system including clock control logic further including a delay block and test logic. The delay block delays a selected number of transitions of a first clock signal to provide a second clock signal, where each selected transition of the second clock signal is delayed, based on a sync signal, by either one of a default skew amount and a programmed skew amount. The test logic enables dynamic control of the sync signal and dynamic programming of the selected skew amount.

Abstract: A hardware-based random number generator is provided for incorporation within an integrated circuit. The random number generator includes a first variable frequency oscillator, a second variable frequency oscillator, and frequency variation logic. The first variable frequency oscillator generates a first oscillatory signal at a first frequency. The second variable frequency oscillator generates a second oscillatory signal that is asynchronous to the first oscillatory signal and has a second frequency less than the first frequency. Bits of the random number are configured from samples of the first oscillatory signal taken at the second frequency. The frequency variation logic is coupled to the second variable frequency oscillator. The frequency variation logic generates a noise signal that directs the second variable frequency oscillator to vary the second frequency.

Abstract: An apparatus and method are provided for testing memory circuits in a microprocessor. The apparatus includes test management logic and test execution logic located within the microprocessor. The test management logic has a non-specific test program stored therein, and it accepts test parameters provided by an external test controller. The test parameters are applied to the non-specific test program to produce a specific test program by inserting the test parameters in place of a plurality of non-specific test operands. The test execution logic executes the specific test program to test the memory circuits within the microprocessor at the internal speed of the microprocessor.

Abstract: A complementary input dynamic logic circuit for evaluating a complex logic function including complementary input dynamic logic circuits, P-channel devices, an inverter/driver for providing an inverted clock signal, and N-channel pass devices. Each complementary input dynamic logic circuit determines a complementary AND function for a corresponding one of multiple sets of AND terms and indicates the complementary AND function via a corresponding one of multiple preliminary evaluation nodes. The P-channel devices are coupled in series between a source voltage and an output evaluation node. Each series-coupled P-channel device has a gate coupled to a corresponding preliminary evaluation node. The N-channel pass devices are coupled in parallel between the output evaluation node and the inverter/driver. Each N-channel pass device has a gate coupled to a corresponding preliminary evaluation node.

Abstract: A digital level shifter for driving the input of a scaled P-channel driver device within a voltage shifted range to preclude gate-oxide breakdown of the scaled driver device. The scaled driver device has an output operative within an elevated voltage range, so that the voltage shifted range biases the voltage associated with a logic signal from a lower voltage level to an intermediate level to preclude gate-oxide breakdown and protect the scaled driver device. The digital level shifter is implemented using digital devices thereby avoiding analog bias devices. The digital level shifter and the scaled driver device may be implemented on the same integrated circuit (IC) and fabricated using the same process as core circuitry so that the IC may directly interface external devices operating at elevated voltage levels without damaging the core circuitry or the scaled driver device.

Abstract: An apparatus and method are provided to enable programmable page table accesses in a virtual memory system. The apparatus includes context logic and context configuration logic. The context logic designates an entry within a data structure. The context logic has a plurality of fields, where each of the plurality of fields provides part of a pointer to the entry. The context configuration logic is coupled to the context logic. The context configuration logic prescribes the structure of the each of the plurality of fields. Programming the context configuration logic determines the function by which the context logic derives a useful value from a virtual address associated with an event.

Abstract: An apparatus is presented for expediting the execution of address-dependent micro instructions in a pipeline microprocessor. The apparatus computes a speculative result associated with an arithmetic operation, where the arithmetic operation is prescribed by a preceding micro instruction that is yet to generate a result. The apparatus utilizes the speculative result to configure a speculative address operand that is provided to an address-dependent micro instruction. The apparatus includes speculative operand calculation logic and an update forwarding cache. The speculative operand calculation logic performs the arithmetic operation to generate the speculative result prior to when execute logic executes the preceding micro instruction to generate the result.

Abstract: A frequency variation apparatus is provided for use in a hardware-based random number generator. The frequency variation apparatus includes sampling frequency variation logic and a sampling frequency oscillator. The sampling frequency variation logic produces a noise signal that corresponds to parity of two independent and asynchronous oscillatory signals. The sampling frequency oscillator is coupled to the sampling frequency variation logic. The sampling frequency oscillator receives the noise signal, and varies a sampling frequency within the random number generator in accordance with the noise signal.

Abstract: An apparatus and method are provided for accurately predicting the outcome of branch instructions prior to their execution by a pipeline microprocessor. The apparatus includes a first table, a second table, and selection logic. The first table stores branch histories for a first set of branch instructions where the first branch instructions are categorized within the first table according to a first outcome bias. The second table stores branch histories for a second set of branch instructions, where the second branch instructions are categorized within the second table according to a second outcome bias. The selection logic is coupled to the first and second tables. When a branch instruction is executed by the microprocessor, the selection logic selects a particular branch history to predict the outcome of the branch instruction.

Abstract: An apparatus and method are provided that enable a central processing unit (CPU) to extend the attributes of virtual memory beyond that which an existing translation lookaside buffer within the CPU is capable of storing while at the same time preserving compatibility with legacy operating system software. The apparatus includes a translation lookaside buffer and extended attributes logic. The translation lookaside buffer (TLB) stores a plurality of TLB entries. Each of the TLB entries has an extended memory attributes index field. The extended attributes logic is coupled to the TLB. The extended attributes logic employs the extended memory attributes index field to access one of a plurality of extended memory attributes registers that is external to the TLB. Contents of the extended memory attributes register prescribe specific extended properties for a corresponding virtual memory page.

Abstract: An apparatus and method are provided for executing a combined compare-and-branch operation in a single integer pipeline microprocessor. Typically, the compare-and-branch operation is specified by two macro instructions. The first macro instruction, a compare macro instruction, directs the microprocessor to compare two operands, resulting in the update of a flags register to describe various attributes of the comparison result. The second macro instruction, a conditional jump macro instruction, directs the microprocessor to examine the flags register and to branch program control to a target address if a prescribed condition is met. The apparatus has translation logic that combines the compare macro instruction and the conditional jump macro instruction into a single compare-and-branch micro instruction. The single compare-and-branch micro instruction directs the microprocessor to make the comparison and to perform a conditional branch based upon a result of the comparison.