Abstract: An apparatus and method for performing integer division in a microprocessor are provided. The apparatus includes translation logic, floating point execution logic, and integer execution logic. The translation logic decodes an integer divide instruction into an integer divide micro instruction sequence and an overflow detection micro instruction sequence. The integer divide micro instruction sequence is routed to and executed by the floating point execution logic. The overflow detection micro instruction sequence is routed to and executed by the integer execution logic. The integer execution logic and the floating point execution logic execute the overflow detection micro instruction sequence and the integer divide micro instruction sequence concurrently.

Abstract: A microprocessor is provided for executing a floating point exchange micro instruction sequence to swap the contents a first location and a second location. The microprocessor includes register/control logic that receives a floating point micro instruction, determines that the contents of the first location depend upon resolution of a preceding floating point micro instruction, and provides a signal indicating the dependency. The microprocessor also has interlock logic that, in the event of a dependency forwards a new target location to the preceding floating point micro instruction. The microprocessor also includes target location modification logic that receives the new target location and for provides the new target location to the preceding floating point micro instruction. Modification of the target location allows the floating point exchange micro instruction sequence to execute without resolution delay.

Abstract: An apparatus and method for recording a floating point macro instruction error pointer within a microprocessor is provided. The apparatus includes translation/control logic for generating a micro instruction sequence to perform a floating point operation. The micro instruction sequence includes a first micro instruction, inserted in the sequence in place of a translate slip, which directs the microprocessor to store a first part of the floating point macro instruction error pointer associated with a floating point macro instruction. The micro instruction sequence also includes a micro instruction extension, associated with a floating point micro instruction within the sequence. The extension directs the microprocessor to store a second part of the floating point macro instruction error pointer. The error pointer is stored in zero effective time increments without requiring additional hardware.

Abstract: An apparatus and method for loading aligned/misaligned data from a cache within a microprocessor is provided. The apparatus contains a first ALU for generating a partial offset, alignment check logic for quickly estimating the alignment of the data, a second ALU for generating a linear address, and alignment confirmation logic for confirming the alignment of the data. Quick estimation of data alignment allows the load of data to proceed before full alignment calculations are completed. A mandatory slip during data alignment checking is eliminated.