Abstract: Disclosed is an integrated microprocessor chip. The chip includes a digital video decoder Inverse Discrete Cosine Transform element and an on chip Read Only Memory. The on chip Read Only Memory includes (a) a shift register latch for receiving data from off chip pull-up resistors, (b) a register for storing data, (c) a selector and a decoder for selecting memory cells to be read from the register, and (d) a Read Only Memory data output.

Abstract: A method of forming a diffusion barrier on an article of a polymer blend of (i) a high surface energy polymer and (ii) a low surface energy polymer. Most commonly the low surface energy polymer is an organosilicon polymer, as a polysilane or a polysiloxane. The surface of the article is exposed to ozone and ultraviolet radiation to form a diffusion barrier.

Abstract: Disclosed is a Data Valid/Finish circuit element, an integrated circuit using the element, and a method of using the element. The circuit element, which may be incorporated in high speed, digital integrated circuit chips, has an input for receiving input from a data stream, and outputs. One of the outputs is an output true for generating a logical "1" when the input is a logical "1". The other output is an output complementary means for generating a logical "1" when the input is a logical "0". The system logically combines the outputs through an output finish/clock for receiving and combining the outputs of the output true and the output complementary. This generates a logical signal when the input from the data stream is either a logical "0" or a logical "1".

Abstract: A data processing system gives an application running on the operating system exclusive ownership of a hardware device. The system is operable in two modes. In the first mode the application interacts with the hardware device by making use of the processing system. In this mode many layers of the processing system are involved and the interaction time with the hardware is slow and inconsistent. In the second mode, exclusive ownership of the hardware device is granted to the application by the driver. In this mode the application has direct access to the hardware device thus avoiding the involvement of the processing system layers. The application accesses and uses the driver through a low latency processor interface linked into the application program itself.

Abstract: Disclosed is a digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals. This is accomplished with a minimum of DRAM demand through the use of a Spill Buffer.

Abstract: Method and apparatus for calculating motion vectors. The method and apparatus calculate a motion trajectory value and initial base weights such that when x is the horizontal offset of the current macroblock from the left edge of the search window, and y is the vertical offset of the current macroblock from the top edge of the search window, and this pair of x and y values are used as the initial base weights, the motion estimation provides the best matched macroblock that has the shortest distance from the current macroblock. When the initial base weights are set to 0's, then the motion estimation will produce the first best matched macroblock encountered by the search circuitry. A scheme is also provided to set the initial base weights so that the best matched macroblock closest to the motion trajectory is selected for the motion estimation.

Abstract: Solder interconnection encapsulant, encapsulated structure and method for its fabrication and use, whereby the gap created by solder connections between a carrier substrate and a semiconductor device is filled with a composition obtained from curing a preparation containing a cycloaliphatic polyepoxide and/or curable cyanate ester or prepolymer thereof; filler, e.g., an aluminum nitride or aluminum oxide filler, having a maximum particle size of 31 microns.

Abstract: Disclosed is a method of forming a bidirectionally coded picture, i.e., a B frame, from two reference pictures, e.g. I or P frame pictures. The method utilizes a single memory fetch of each reference picture, and interpolation of the estimated motion of each picture. This is accomplished by identifying a full pixel closest match from three full pixel boundary searches, calculating half pixel reference picture data therefrom, interpolating the half pixels to form bidirectionally coded pictures, and finding the closest match at the half pixel boundary. The intermediate results are stored in an 18.times.18.times.11 bit buffer holding a 7 bit partial sum for each pixel, said partial sum formed by adding the six most significant bits of corresponding I and P frame pixels. In this buffer four bits of each word in the buffer are the two Least Significant Bits of the corresponding I and P frame pixels.

Abstract: Disclosed is a digital video encoder processor for discrete cosine transform encoding. The discrete cosine transform encoding includes the encoding steps of (1) determining the discrete cosine transform field or frame type, (2) addressing individual pixels as either (i) vertically adjacent pixels on consecutive Odd and Even field lines, or (ii) vertically adjacent pixels on consecutive Odd field lines, then consecutive Even field lines; or (iii) vertically adjacent pixels on consecutive Even field lines, then consecutive Odd field lines. These subtractions may be performed between (i) consecutive lines, (ii) odd lines, or (iii) even lines. The next step is finding the smallest variance of the above subtractions to determine the discrete cosine transform coding type. The subtractions are carried out in a dynamically partitionable processor having a plurality of datapaths.

Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.

Abstract: A computer system, and its parallel and serial implementations, its serial and parallel network and multi-processor configurations, with tight and loose coupling among processors. The computer system has a CAM coupled to the computer system or imbedded therein. CAM requests may be processed serially, or as parallel queries and coupled with PAPS (Parallel Associative Processor System) capabilities (P-CAM). The computer system may be configured as an expert system preferably having combined tuple space (TS) and CAM (content addressable memory) resources, an inference engine and a knowledge base. As an expert system, improvements for production processing are provided which surpass prior art performance represented by RETE and CLIPS. An inferencing process for production systems is disclosed, and a process for working memory element assertions.

Abstract: Disclosed is an integrated system for creating a process model and writing software based on the process model. The integrated system includes three subsystems, a group decision support subsystem, an applications development subsystem, and a bridge subsystem. The group decision support subsystem is used for creating and ordering a process model according to a protocol. The application development subsystem is used for writing software based on the output of the group decision support subsystem. The bridge sub-system converts the output of the group decision support subsystem to compatible input of the application development subsystem.

Abstract: A digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals includes a FIFO Data Buffer, a RAM having (1) a compressed, encoded Data Buffer and (2) a data portion for storing decompressed digital video buffer data. A Memory Management Unit is provided for managing the RAM.

Abstract: Disclosed is a printed circuit board and a method of preparing the printed circuit board, The printed circuit board has two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component pin. The second type of plated through holes are for surface mount technology and terminate below the exterior surface of the printed circuit board. These plated through holes contain a fill composition.

Abstract: A method and apparatus for parallel "normalize-round-normalize" floating point arithmetic. The rounding-normalizer of the invention receives as an input an infinitely precise mantissa which is the result of a floating point operation. This infinitely precise result mantissa is broken into two fields, the Close Enough Bits, and the Picky Bits. These bits are selectively passed to four parallel data paths for taking close enough bits and picky bits and producing a correctly rounded mantissa. The paths are, respectively; (a) a 1X.XX . . . X data path for mantissas greater than or equal to 2 but less than 4, the data path right shifting the upper bits and adjusting the exponent by +1 or +2; (b) a 01.XX . . . X data path for mantissas greater than or equal to 1 but less than 2, the data path right shifting the upper bits and adjusting the exponents by +0 or +1; (c) a 00.1X . . .

Abstract: Disclosed is a design tool and a method of fabricating a multi-layer printed circuit board. The method utilizes the design tool. The knowledge base means has both (1) printed circuit board cross sectional geometric parameter to transmission line parameter data and (2) "IF . . . THEN . . . " production rules for lamination, registration, circuitization, testability, test tools, and test procedures. These tools relate to manufacturability, cost, test development, second level packaging and printed circuit board. The printed circuit board begins with the user entering the printed circuit board design parameters and performance parameters into the input/output interface. Next, the knowledge base production rules are applied to the printed circuit board design and performance parameters to generate a set of cross section designs meeting the user specified parameters. The printed circuit board is then built up in accordance with one of the generated cross section designs.

Abstract: A circuit, as a logic circuit or a memory circuit, having testing latches. The testing latches include an input latch, a slave latch, and true and complement output latches. The output of the slave latch is NANDed with a DESELECT signal to deselect the output latches. The testing latches can be used in a method of characterizing or testing a memory or logic integrated circuit with scannable output latches. At least one output latch has an input latch, a slave latch, and an output latch which may contain a Complement Latch, and a True latch. In the testing process an output of the slave latch is NANDed with a deselect signal to allow testing or characterization by masking known "fail" signals.

Abstract: A method for encoding bitstream headers in a processor where templates for the bitstream header are stored in a processor buffer. The templates are addressable by programmable instructions, and the processor has a status register containing a bit for each header type. The status register is modifiable during the encoding process with a data pattern indicating the headers needed for encoding with the bitstream. In this way when a bit is set to 1 the predefined header type is generated and shipped to the bitstream. The header is generated by processing the header buffer template entries associated with the header type.

Abstract: A computer system with an image reader and nerual network is provided for determining whether an image of text has been generated by a machine or by hand. This serves the useful purpose of allowing one to use speciallized recognition techiques that are more suited to one form of printing, thus achieving a higher recognition accuracy than by using a single recognition technique for both types of printing. The method is based on the premise that the spatial spectra for an image of machine text will have more higher frequency components than one generated by hand, because of the nonregular, nonuniform slant of the handprint. The method proposed generates this spectra by convolving spatial templates with vertical histograms from each line of text, and uses a neural network to classify the resulting spectra.