Abstract: Disclosed is a design tool and a method of fabricating a multi-layer printed circuit board. The method utilizes the design tool. The knowledge base means has both (1) printed circuit board cross sectional geometric parameter to transmission line parameter data and (2) "IF . . . THEN . . . " production rules for lamination, registration, circuitization, testability, test tools, and test procedures. These tools relate to manufacturability, cost, test development, second level packaging and printed circuit board. The printed circuit board begins with the user entering the printed circuit board design parameters and performance parameters into the input/output interface. Next, the knowledge base production rules are applied to the printed circuit board design and performance parameters to generate a set of cross section designs meeting the user specified parameters. The printed circuit board is then built up in accordance with one of the generated cross section designs.

Abstract: A computer system, and its parallel and serial implementations, its serial and parallel network and multi-processor configurations, with tight and loose coupling among processors. The computer system has a CAM coupled to the computer system or imbedded therein. CAM requests may be processed serially, or as parallel queries and coupled with PAPS (Parallel Associative Processor System) capabilities (P-CAM). The computer system may be configured as an expert system preferably having combined tuple space (TS) and CAM (content addressable memory) resources, an inference engine and a knowledge base. As an expert system, improvements for production processing are provided which surpass prior art performance represented by RETE and CLIPS. An inferencing process for production systems is disclosed, and a process for working memory element assertions.

Abstract: A pipeline floating point processor in which the addition pipelining is reorganized so that no wait cycle is needed when the addition uses the result of an immediately foregoing multiplication (fast multiply-add instruction). The reorganization implies the following changes of an existing data flow of the pipeline floating processor: data feed-back via path ND of normalized data from the multiplier M into the aligners AL1 and AL2; shift left one digit feature on both sides of the data path for taking account of a possible leading zero digit of the product, and special zeroing of potential guard digits by Z1 and Z2; exponent build by 9 bits for overflow and underflow recognition, and due to an underflow the exponent result, is reset to zero on the fly by a true zero unit (T/C).

Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.

Abstract: A self-checking complementary adder unit used for high performance subtractions comprises two carry select adders (30 and 36) each of which consists of a pair of byte or digit organized ripple carry adders (31, 32 and 37, 38) generating in parallel virtual sums from true and complemented operands based on the assumption that the carry-in signal is 1 or 0. Depending on byte or digit carry signals generated by carry look ahead circuits (33, 39), partial sums are selected from the virtual sums to form a real sum. The outputs of both carry select adders are connected to a multiplexer (42) which is controlled by the high order carry-out signal from one of the carry look ahead circuits representing the sign of a real sum. The multiplexer selects one of the real sums as the result of a subtraction. A sum checker compares cross-wise the parity bits of the virtual sums from both carry select adders and also compares the related carry-out signals from both the ripple carry adders and carry look ahead circuits.

Abstract: Disclosed is a test method and system for boundary testing a circuit network. The network, made up of individual integrated circuit chips mounted on a printed circuit card or board, has at least one integrated circuit that is testable by IEEE 1149.1 Standard boundary testing, and at least one second integrated circuit that is testable by Level Sensitive Scan Design boundary testing but not by IEEE 1149.1 Standard boundary testing. The test system has a test access port interface with a test access port controller with Test Clock, Test Data In, Test Data Out, Test Mode Select, and Test Reset I/O. The test access port also has an instruction register, a bypass register, a test clock generator, and a Level Sensitive Scan Device boundary scan register.

Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.

Abstract: Disclosed are methods and apparatus for a testing a field programmable logic gate array. In the method the non-volatile gates are set to a testable setting. The programmable logic array is then configured into (1) a pseudo random pattern generator, (2) a multiple input signature register, (3) a signature comparator, and (4) AND-plane and OR-plane logic array areas. A pseudo random set of test pattern vectors is applied to the programmable logic array from the pseudo random pattern generator. The output is captured in the multiple input signature register and compared in the comparator. Finally, individual non-volatile floating gate field effect transistors are selectively set to provide the desired set of sums of products.

Abstract: Disclosed is a printed circuit board and a method of preparing the printed circuit board. The printed circuit board has two types of plated through holes. The first type of plated through holes extend to and through an exterior surface of the printed circuit board for receipt of a pin-in-through-hole module or component pin. The second type of plated through holes are for surface mount technology and terminate below the exterior surface of the printed circuit board. These plated through holes contain a fill composition.

Abstract: Disclosed is a manufacturing system having isolated islands of "clean room" environment connected by inter-process transfer containers for transfering in-process workpieces. The system has airlock transfer ports between the process enclosures and the inter-process transfer containers. The make and break airlock transfer ports have facing sealable doors in the process enclosure and the transfer container. These doors are in air sealable facing recesses of the process enclosure and the transfer container. At least one peripheral gasket surrounds the recesses and the pair of doors. This provides a substantially clean room environment in the airlock. The sealable door in the interprocess transfer container is fabricated of a ferromagnetic material and is seated on a ferromagnetic gasket, while the sealable door in the process enclosure has a controllable electromagnetic clamp.

Abstract: Disclosed is a test system for printed circuit boards and more particularly a test system having machine vision locating of the printer circuit board above the tester, and telescoping test probe pins extending through a multilayer test probe pin guide. Also disclosed is a method of testing printed circuit boards using the test system.

Abstract: Disclosed is a method of laminating circuitized polymeric dielectric panels with pad to pad electrical connection between the panels. This pad to pad electrical connection is provided by a transient liquid phase formed bond of a joining metallurgy characterized by a non-eutectic stoichiometry composition of a eutectic forming system. The eutectic temperature of the system is below the first thermal transition of the polymeric dielectric, and the melting temperature of the joining metallurgy composition is above the first thermal transition temperature of the polymeric dielectric.

Abstract: A method of testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip test fixture system is provided. The chip test fixture system has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into electrically conductive contact with the conductor pads on the chip test fixture system. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing the chip is removed from the substrate.

Abstract: Disclosed is a high solidus temperature, high service temperature, high strength ternary solder alloy. The components of the alloy are a major portion of Sn and lesser portions of Bi, and In.

Abstract: A high solidus temperature, high service temperature, high strength multi-component solder alloy having a major portion of Sn and effective amounts of Sb, Bi and Cu.

Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.

Abstract: A method of defining, creating, or editing a menu bar in a graphical user interface panel file for a graphical user interface panel. The method includes opening a graphical user interface source code file, and entering at least one menu bar defining tag file. The menu object tag file is then edited and compiled to form an edited graphical user interface object code file including a menu bar.

Abstract: An optical inspection system is provided in which the background video component of an analog video source which limits imaging integrity is removed enhancing the system's ability to process a wider range of image sources with increase digitizing sensitivity. The overall effects of background and background variations are nulled stabilizing the effective signal to noise ratio, thereby increasing inspection capability of the system and improving the system's process window for effective and efficient inspection.

Abstract: Disclosed is a system for handling large area, in-process, circuit panel layers. The circuit panel layers are thin and flimsy, and require rigid support for certain processing steps. The system includes a peripheral frame fixture for surrounding and supporting the in process circuit panel layer, and a a loading chuck for mounting the in-process circuit panel layer in the peripheral frame fixture. The peripheral frame fixture includes a bottom plate having a central opening to expose the circuit panel layer, a top frame having a corresponding central opening to expose the opposite surface of the circuit panel layer, and a compressive apparatus, as screws, bolts, or the like, for applying a z axis compressive force to the bottom plate, the top frame, and a panel layer therebetween. Optionally, the fixture may include alignment pins or fiducials for aligning the bottom plate, a panel layer, and the top frame, and a robotic interface for a robotic arm to grasp and transfer the peripheral frame fixture.

Abstract: Disclosed is a method of populating printed circuit boards with surface mount technology devices in a multi-board work board holder. The method includes the steps placing the printed circuit boards into a multi-board work board holder having a plurality of apertures corresponding to the individual printed circuit boards. The multi-board work board holder is placed onto a surface mount technology production line, and solder paste is selectively applied onto contact pads on surfaces of the printed circuit boards. Integrated circuit chips are next placed onto the solder paste bearing surface of the printed circuit boards, with the contact leads of the integrated circuit chips bearing on deposited solder paste. The printed circuit boards and the work board holder are heated to the reflow temperature of the solder.