Abstract: A method for controlling oxygen precipitation (106) in a silicon crystal (12) grown according to the Czochralski silicon crystal growing technique which includes the steps of forming a cylindrical portion (22) of the silicon crystal (12) from a reservoir of molten silicon (24) according to the Czochralski silicon crystal growing technique. The method includes the steps of terminating the Czochralski silicon crystal growing technique by forming a first tapered portion (101) in silicon crystal (12) at a predetermined rate. A second tapered portion (102) includes a cascaded middle portion (108) that connects to the first tapered portion (101) and that concentrates oxygen precipitation (106) within cascaded middle portion (108) and away from the cylindrical portion (22) of silicon crystal (12). At least a third tapered portion (104) is formed for separating silicon crystal (12) from molten silicon (24).

Abstract: This invention is a voltage divider circuit having an input voltage at a first terminal (V.sub.IN) and an output voltage at a second terminal (V.sub.OUT). The circuit includes a parallel-connected first resistor (R.sub.1) and first capacitor (C.sub.1) coupled between the first and second terminals (V.sub.IN,V.sub.OUT) and a parallel-connected second resistor (R.sub.2) and second capacitor (C.sub.2) coupled between the second terminal (V.sub.OUT) and a reference (V.sub.REF). The ratio of the ohmic value of the second resistor (R.sub.2) to the sum of the ohmic values of the first and second resistors (R.sub.1,R.sub.2) is substantially equal to the ratio of the value in farads of the first capacitor (C.sub.1) to the sum of the values in farads of the first and second capacitors (C.sub.1,C.sub.2).

Abstract: A gate array structure includes a plurality of transistors (21-47) interconnected to form a two-bit memory cell. First and second interconnected transistors of the plurality are respectively provided in adjacent base sites (51, 53) of the gate array structure.

Abstract: A method for detecting defects between parallel rows of conductors (ROW) in an integrated-circuit array (ARR) includes (a) connecting all alternate rows (ROW) of conductors of the array (ARR) to a first voltage (V.sub.DD) and connecting the other alternate rows (ROW) of conductors of the array (ARR) to a second voltage (V.sub.REF) different from the first voltage, while measuring the current drawn; (b) if the current does not exceed a first limit, ending the process; (c) if the current exceeds the first limit, separately repeating step (a) on first and second halves of the array rather than all of the array, with all of the rows (ROW) of conductors of the half of the array (ARR) not under test connected to the second voltage (V.sub.REF); (d) if the current exceeds a second limit for a half of the array (ARR) in step (c), repeating step (a) on each quarter of the array (ARR) in that half with all of the rows (ROW) of the array (ARR) not under test connected to the second voltage V.sub.

Abstract: The circuit of this invention includes a programmable circuit (PC) for storing an internal address and for producing logic levels (LL1, etc.) determined by that internal address and includes a first comparison circuit (CC1) and a second comparison circuit (CC2). The first comparison circuit (CC1) responds to the logic levels (LL1, etc.) representative of that internal address and to a first address signal (CA0, etc.) to generate a first match signal (CRFSN) determined by matching of the internal address and the first address signal (CA0, etc.). The second comparison circuit (CC2) responds to the logic levels (LL1) and to a second address signal (SF0, etc.) to generate a second match signal (SRSJN) determined by the matching of the internal address and the second address signal (SF0, etc.).

Abstract: Semiconductor die attach occurs by bonding the semiconductor die to a support member such as a lead frame. An optical heat source provides heat for bonding the die attach material. An exhaust system removes vapors from the die attach material during bonding. A tungsten halogen lamp is an exemplary optical heat source. An air amplifier is exemplary to provide exhaust pressure. An exhaust manifold having a plurality of screens spreads the exhaust pressure over the width of the lead frame. A gas shower disposed over the lead frame aids in removing vapors.

Abstract: Reference circuitry RC includes a current-sensing translator M5-M7, MX connected to a current reference source RS. The outputs O1, O2, etc. of the current-sensing translator M5-M7, MX are mirrored into one or more sense amplifiers SA1,SA2 of sensing circuitry SC. The current-sensing translator M5-M7, MX permits the current from the current reference source RS to be mirrored to multiple sense amplifiers SA1,SA2 at a predetermined ratio.

Abstract: An output buffer includes a pair of P-channel transistors and two cascode pull-down N-channel transistors to drive an output node. The output pull-up transistor has the gate thereof connected through a P-channel control transistor to an input driving signal. The control signal is isolated from the output node by a P-channel transistor which only conducts during overvoltage conditions. During normal operation, the control transistor is maintained in a conductive state to allow the gate of the output pull-up transistor to be pulled high and low. During an overvoltage condition, the P-channel transistor connected between the output node and the control transistor is turned on in order to effectively turn off the control transistor. The P-channel transistors in the output buffer are floating well-type transistors with the wells thereof tied to a switched voltage that is either the supply voltage during the normal operating mode or the output node during overvoltage conditions.

Abstract: An integrated circuit memory cell (10) is formed with a P-N junction polycrystalline floating gate (13) with a lightly boron doped on the source side (13B) and a heavily arsenic or phosphorous doped on the drain side (13A) plus the channel region (Ch) . The cells (10) are formed in an array at a face of a semiconductor body (22), each cell including a source (11) and including a drain (12). An improved over-erase characteristic is achieved by forming a P-N junction (JU) in the floating gate (13). Use of a P-N junction (JU) in polycrystalline floating gate (13) prevents the cell (10) from going into depletion, causes a tighter distribution of erased threshold voltages V.sub.T, and improves device life because fewer electrons travel through the gate oxide (30).

Abstract: A semiconductor random access memory having a complex topology is provided with ROM unit storing every potential row data pattern to be entered in the storage cell array during a test procedure, a variable step address generator, a comparator mechanism, and a control unit. In response to signals from the control unit, the variable step address generator enters each row data pattern at appropriate addresses determined by the periodicity of the complex topography. The variable step address generator is then used to retrieve stored data groups from addresses used to store each ROM data pattern. The retrieved data groups are compared with the ROM data pattern used as a template for the stored data group. A record of the comparison errors can be stored in an erasable memory unit.

Abstract: A semiconductor memory is disclosed having a primary memory array (12) and a dummy column (14) associated therewith that is comprised of a plurality of dummy memory cells (70). The dummy memory cells have a predetermined value stored therein and are sensed with a dummy sense amplifier (18). The dummy sense amplifier (18) has a predetermined offset disposed therein, such that it is in a predetermined state prior to the bit lines separating a sufficient amount to detect the logic state in the dummy memory cell, with an offset disposed therein. This offset prevents the state of the dummy sense amp from being changed until the bit lines are separated by a predetermined value. The primary sense amplifiers associated with the primary memory array (12) are not enabled until the dummy sense amplifier has detected the dummy bit lines as being separating by the predetermined amount.

Abstract: An EPROM or flash EEPROM, which has an array of single-transistor, stacked-gate, memory cells. Active areas for transistor elements are in columns up and down the array, with columns being isolated by thick field oxide strips (220). Word lines (236) and source lines (212) run across the array. Bit lines (216) run along the active area columns to connect transistor drains (218). Bit lines are perpendicular to word lines. Each stacked gate includes a control gate (232) and a floating gate (230), with the latter having a top portion (230b) and a bottom portion (230a) that are separately deposited and etched. The bottom portion (230a) is etched in strips along the active area columns, and define the gate width of each cell. The top portion (230b) overlaps the bottom portion (230a) to improve capacitance between control gate (232) and floating gate (230).

Abstract: An electronic system 8 is disclosed herein. The system includes circuitry 10 for processing a signal and a plurality of antennas 12a-12b. A plurality of switches 22a-22b are also included. Each of the switches 22a-22b is coupled between the processing circuitry 10 and a corresponding one of the antennas 12a-12b. Each of the switches 22a-22b includes first and second power MOSFETs where the source of the first MOSFET is coupled to the source of the second MOSFET. The system further includes circuitry 28 for selecting of one of the plurality of switches 22a-22b to be on.

Abstract: The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro-instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM) to select instructions from the control-read-only-memory, a micro-instruction decoder with BILBO control (MID/BC), a test input multiplexer (TIM) to test control signals, an optional status output register (SOR) to generate control signals, and a subroutine stack (SS) to allow function calls. A program counter (PC) takes an index signal from the micro-instruction decoder with BILBO control (MID/BC) and a signal from the program counter multiplexer (PCM), and from those signal, generates a next microcode address. Complex program, erase, and compaction instructions for the integrated-circuit memory are implemented using a relatively small number of control-read-only-memory locations and using a relatively small surface area on the memory chip.

Abstract: An insulated-gate field-effect transistor 10 is formed on a semiconductor substrate 8. The source 12 and/or drain 20 junction region comprises a heavily doped region 14 (22), a non-overlapped lightly doped region 16 (24), and an overlapped lightly doped region 18 (26). The doping concentration and junction depth of the overlapped 18 and non-overlapped 16 lightly doped regions may be controlled and optimized independently. An insulating layer 50 is formed over a channel region 28 which separates the source 12 and drain 20, and also over the overlapped portions of the source 18 and drain 26. A gate 42 is formed over the insulating layer 50. Two exemplary methods of fabrication are disclosed in detail herein as well as other systems and methods.

Abstract: A circuit is designed with a decoder circuit (10), responsive to a first input signal (81) having a first voltage range, for producing a first output signal. An output circuit (11), responsive to the first output signal, produces a second output signal (26) having a second voltage range. The second voltage range includes a voltage less than a least voltage of the first voltage range and a voltage greater than a greatest voltage of the first voltage range.

Abstract: A high voltage power transistor cell is developed that provides improved RDSon performance without sacrificing breakdown performance through utilization of trench based transistor technology. A source, drain and trench are formed within a substrate. A gate is formed on the surface over a spacing between the source and the trench. A drift region is formed around the trench. An isolation region may optionally be added allowing electrical isolation between the source and the substrate. The lateral current flow feature allows multiple high voltage power transistors, electrically isolated from one another, to exist on a single semiconductor chip. The drift region formed around the trench provides RESURF transistor characteristics without sacrificing die area.

Abstract: A supply-voltage detecting stage (11) that supplies first and second reference currents (I.sub.REFP and I.sub.REFN) which vary with the supply voltage (V.sub.cc) and are coupled by first and second gain stages (12A and 12B), respectively, to first and second temperature-detecting stages (13A and 13B), respectively. First and second temperature-detecting stages (13A and 13B) increase the coupled reference currents (I.sub.REFP and I.sub.REFN), respectively, to compensate for temperature increase through use temperature-sensitive, long-channel transistors (M34-M37 and M42-M45), supplying temperature and supply-voltage compensated output bias voltages at output terminals (MIRN and MIRP).

Abstract: A System and method for calibrating a chip after packaging including providing a packaged chip, providing programmable non-volatile storage having a plurality of non-volatile storage elements in the chip and providing a volatile storage having a plurality of volatile storage elements in the chip with one volatile storage element associated with one non-volatile storage element. The chip includes circuitry responsive to a predetermined signal to permit the non-volatile storage to be programmed in accordance with data stored in the volatile storage and to a predetermined signal to prevent external alteration of the non-volatile storage. The non-volatile storage is preferably a plurality of fuses. The volatile storage is preferably a shift register.

Abstract: A method of forming a microelectronic device is described comprising the steps of providing a substrate, forming a conductive region on the substrate, and forming an insulating layer on said conductive region and said substrate. The method further comprises the steps of forming a spacer layer on said insulating layer, removing selective portions of said spacer layer and said insulating layer to expose a selective area of said conductive region thereby forming a storage node contact window, and forming a first conductive layer on said spacer layer and within said storage node contact window wherein said first conductive layer is in electrical communication with said conductive region.