Abstract: A patternless, self-aligning method of forming a floating gate on a silicon wafer having a plurality of raised field oxide isolation structures. The method of the present invention includes depositing a polysilicon layer onto the silicon wafer and the raised field oxide isolation structures, depositing a polysilicon etch masking layer onto the polysilicon layer, and planarizing the polysilicon etch masking layer. The polysilicon etch masking layer is then etched to expose the polysilicon layer over the raised field oxide isolation structures. The exposed polysilicon layer is then etched to remove the polysilicon layer over the raised field oxide isolation structures. The remaining polysilicon etch masking layer is then removed, leaving a plurality of polysilicon regions covering the silicon wafer between the field oxide isolation structures.

Abstract: A reduced silicon area, wide input/output (I/O) comparitor method and apparatus for design-for-test applications includes a plurality of input/output pins (60) and plural arrays of addressable storage cells (32-46). A page mode writing circuit provides, through a common data-in lead (30), plural copies of a test data bit, applied through one of the pins (30), for storage in addressed storage cells (32-46) along a row in each of the arrays of storage cells. A circuit receives an expected data bit (ED), and a readout circuit reads out the stored test data bit from the addressed storage cells along the row in each of the arrays of storage cells. A PRW signal generator (154) responds to a column address change to establish a first potential state on all four quadrant-specific common lines (102, 408, 411, and 413).

Abstract: In a dynamic random access memory unit 10, a circuit, 61.sub.0 -61.sub.N.sbsb.--.sub.1, 615, and 617, is provided in which a non-change of each address signal of an address signal group during a next consecutive clock cycle blocks the application of the read activation control signal to the memory unit 10. In this manner, the memory unit 10 is inactive (i.e., does not perform a read operation) during the modify portion of a read-modify-write operation so that potential conflicts in the operation of the memory unit 10 are avoided.

Abstract: An integrated circuit includes a conductive structure (66) is formed with a top layer of silicon nitride (62) and silicon nitride (70) sidewalls on a semiconductor substrate. The layer of silicon nitride (70) covering the sidewalls of the conductive structure (66) intersect with the layer of silicon nitride on top of the conductive structure with a relatively square shoulder. A subsequently deposited conductor makes contact with the surface of the semiconductor substrate (56) without shorting to the conductive structure (66) on the semiconductor substrate.

Abstract: A surface plasmon resonance sensor includes a light source 10 and a polarizer 18 for producing polarized light which passes through a transparent body 12 and strikes a thin conductive film 26 disposed on the exterior surface of the body 12. The film 26 exhibits surface plasmon resonance when the light strikes the film at a "resonance angle". By determining the angle at which surface plasmon resonance occurs, the refractive index of the material on the side of the film 26 opposite to the side which reflects the polarized light can be measured.

Abstract: A memory unit 30 is provided with a first and second sense amplifier array 32A and 32B. The storage cells 31 of the memory unit are coupled to both sense amplifier arrays. A control unit 34 is provided which controls the operation of the two sense amplifier arrays. The control unit determines through which sense amplifier array data signals are transferred to and from the storage cells. The sense amplifier array not exchanging signals with the I/O terminals can perform the precharge operations and write-back operations. Synchronous operation of the memory unit and a data processing unit can be maintained by alternating the sense amplifier array performing the current memory access operation.

Abstract: A modem that operates selectively in the voice-band frequency band and higher frequency bands is provided. This modem supports multiple line codes, like DMT and CAP. The modem uses a Digital Signal Processor (DSP), so that different existing ADSL line codes, such as Discrete MultiTone (DMT) and Carrierless AM/PM (CAP), can be implemented on the same hardware platform. The modem employs a method for interfacing the modem hardware with a host operating system. The method calls a defined set of host interface functions for command/control, calls a defined set of host interface functions for link correction management, calls a defined set of host interface functions for data sending/receiving, calls a defined set of host interface functions for synchronization between voice-band audio and above voice-band audio, and calls a defined set of host interface functions to use the voice-band as control channel and above voice-band as a data channel.

Abstract: A processing system including a vacuum chamber 24 and at least one tube 12 disposed through a wall 14 of the vacuum chamber 24 is described herein. A gas diffuser 22 is disposed in said tube 12, possibly at the end of the tube 12 and/or outside the chamber 24. The gas diffuser 22 is formed from a porous, possibly metallic, material which includes a plurality of microscopic holes whereby gas entering or leaving the vacuum chamber through the tube has a reduced force compared to if the gas diffuser 22 was not present. Other systems and methods are also disclosed.

Abstract: A nonvolatile memory array is encased in a P-well, and the P-well encased in a deep N-well, the two wells separating the memory array from the integrated circuit substrate and from the other circuitry of the integrated circuit. At the same time the deep N-well is formed for the nonvolatile memory array, deep N-wells are formed for the high-voltage P-channel transistors of the logic circuitry. At the same time the P-well is formed for the nonvolatile memory array, P-wells are formed for the low-voltage N-channel transistors. The memory array contains nonvolatile cells of the type used in ultra-violet erasable EPROMs. During erasure, the isolated-well formation allows the source, the drain and the channel of selected cells to be driven to a positive voltage. The isolated well is also driven to a positive voltage equal to, or slightly greater than, the positive voltage applied to the source and drain, thus eliminating the field-plate breakdown-voltage problem.

Abstract: An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate test socket to a separate integrated circuit device that is inserted into the test socket. A device tester is called to the plurality of microcomputers for transmitting information between the device tester and the plurality of microcomputers. Each microcomputer contains instructions and data for performing a test routine on the associated integrated circuit device and transmitting selected results of the test routine to the tester.

Abstract: A method of degating molded parts including the steps of providing a water soluble molding material, molding a configuration from the molding material including parts secured to a runner system by gates of the molding material having a cross-section substantially thinner than any cross-section of the molded configuration, cooling the surfaces of the configuration to a temperature and for a time until only the gates becomes brittle, preferably by spraying liquid nitrogen over the surface of the configuration and applying an impact to the configuration to cause the configuration to sever at the gates, preferably by tumbling the cooled configuration, whereby the severed parts are separated from the runner system.

Abstract: A bi-stable logic device 110 comprises first and second inverters 112 and 114. A first resistive connection 140 is made between the input 134 of the first inverter 112 and the output B.sub.-- of the second inverter 114 and a second resistive connection 142 is made between the input 138 of the second inverter 114 and the output B of the first inverter 112. The first and said second resistive connections are also capacitively coupling. The device 110 is hardened from single event upset. Other systems and methods are also disclosed.

Abstract: During the preconditioning of word lines (19) of a memory array (10), Each nondefective word line (19) is fired, one at a time, to raise the turn-on voltage of the word line. After each nondefective word line (19) has been fired, physically adjacent word line groupings (35) are fired simultaneously without regard to the presence of defective word lines (19).

Abstract: A memory configuration (20) which includes a first and second bank (B0, B1). Both bank arrays comprises a plurality of wordlines (WLs) and bitlines (BLs). The memory configuration further includes a plurality of column decoder circuits (CDEC0-CDEC7), and a plurality of y-select conductors (C0-C15) generally parallel to the plurality of bitlines of the first bank array. Each of the plurality of y-select conductors is operable to be selected by one of the plurality of column decoder circuits in response to a column address. The memory configuration further includes a plurality of column factor conductors (F0.sub.I, F1.sub.I, F2.sub.I) formed in a direct periphery area existing between the first and second bank arrays. Still further, the memory configuration includes a power conductor (PDD.sub.I) formed between the first and second bank arrays, and aligned generally parallel to the plurality of wordlines of the first and second bank arrays.

Abstract: A method of forming a thin film of a metal oxide on a substrate by coating the substrate with a solution comprising metal-organic precursors is disclosed. This method is applicable to, e.g., forming thin films of perovskite-phase titanates, zirconates, and/or niobates of divalent metals such as Ba, Sr, Pb and/or Ca. In one embodiment, a first precursor comprises a divalent metal coordinated to one or more organic ligands, and a second precursor comprises a tetravalent metal coordinated to one or more organic ligands are supplied in a common solution. A substrate 14 is coated with this solution (e.g. by spin coating) to form a preliminary thin film 10. Substrate heater 22 preferably heats substrate 14 to a temperature sufficient to react ligands from the first and second precursors in an ester elimination reaction which forms a volatile precursor 16. This reaction leaves an intermediate compound film 12 comprising the divalent metal and the tetravalent metal on the substrate.

Abstract: A semiconductor static random access memory (RAM) array (10) is disclosed. The static RAM array (10) includes a plurality of memory cells (12), where each memory cell (12) is coupled to a write enable switch (34). The write enable switch (34) responsive to a write enable signal (36) is coupled between each memory cell (12) and a voltage source (27) or a voltage ground (29). The write enable switch (34) can disconnect each memory cell (12) from either the voltage source (27) or the voltage ground (29) responsive to the write enable signal.

Abstract: A light-weight adhesive note recording device (12) records sounds (22) and written text (20) and attaches to a plurality of different types of surfaces (14). Recording circuitry (34) receives and records sounds (22) as a plurality of digital signals. Memory circuitry (38) stores digital signals, and speaker circuitry (40) plays back digital signals as recordings of sounds (22). Control circuitry (36) controls operation of recording circuitry (34), memory circuit (38), and speaker circuitry (40). Power source (44) provides power to operate recording device (12). Text surface (26) is used for writing or printing written text or message (20). Adhering mechanism (54) adheres recording device (12) to a wide variety of surfaces (14). Recording device (12) has sufficiently small size and a flat writing or text surface (26) for repeated use as an adhesive note recording device.

Abstract: A semiconductor memory device 10 having sense amplifiers where the latch transistor moat region width is increased for the same sense transistor pitch. Each sense amplifier comprises latch transistors having a moat region and a gate region comprising a plurality of gate fingers where the length of the gate fingers is determined by the pitch of the sense amplifier. Adjacent latch transistors are offset from one another in both the horizontal and vertical directions and the gate fingers of those latch transistors are interleaved such that the latch transistors have wider moat regions while maintaining the sense amplifier latch transistor pitch. The resulting structure increases the sensing performance while maintaining the pitch.

Abstract: Slew-rate limited differential drivers are useful for reliable data transmission on longer un-terminated cables with longer stub lengths. Slew-rate limit can be achieved by the ratio of a constant current to a capacitor means. In order to have equal rise and fall times, an equal amount of current is steered into the capacitor means in opposite directions. This architecture has unequal propagation delays on the transition edges. This mismatch is directly attributable to the signal transfer in current steering means. The slew-rate limited differential driver corrects this problem by delaying the rising edge by the required amount using a second capacitor means and a diode means. And hence, the preferred embodiment has a better skew on the output.

Abstract: The device and process of this invention provide for eliminating reading errors caused by over-erased cells by applying flash erasing pulses, then flash programming pulses to the cells of an EEPROM array. The flash erasing pulses are sufficient in strength to over-erase the cells. The flash programming pulses applied to the control gates have the same voltages as those used to program individual cells. The strength of the programming electric field pulses adjacent the floating gates is controlled by applying a biasing voltage to one of the source/drain regions of the cells. The biasing voltage controls the energy level of the programming field pulses such that only enough charge is transferred to the floating gates to cause the threshold voltages of the cells to have positive values less than that of a predetermined wordline select voltage.