Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

Abstract: In one embodiment, a kit for reusably attaching an identification transponder 22 to an object 16 to be identified is disclosed. The kit includes an outer sleeve 10, an inner package 12 and, optionally, a release tool 14. The outer sleeve 10 is preferably formed of a non-electrically conducting material and includes an outer locking mechanism 18 disposed therein. The inner package 12 will store the identification transponder 22 and includes an inner locking mechanism 20 for cooperating for with the locking mechanism 18 within the outer sleeve 10. The inner package 12 is operable to be secured within the outer sleeve 10 when the inner locking mechanism 20 and the outer locking mechanism 18 are engaged. If included, the release tool 14 can be used for removing the inner package 12 from the outer sleeve 10 by disengaging the inner locking mechanism 20 from the outer locking mechanism 18.

Abstract: A vertical PNP transistor (11) and method for making it includes forming an N- region (19) in a P substrate (12), and forming an N+ region (26) in the substrate (12) laterally surrounding and partially extending into the N- region (19). A P region (30) is formed above the N- region (19), bounded laterally by the N+ region (26) to be horizontally and vertically isolated from the substrate (12) by the N- and N+ regions (19 and 26). A layer of semiconductor material (32) is formed overall, and an N well (35) and a surrounding P well (36) are formed, each extending to the P region (30). An isolating N+ well (38) is formed surrounding the P well (36), extending to the buried N+ region (26). A P emitter region (40) and an N base contact region (41) are formed at a surface of the N well (35), and a P collector contact region (44) is formed at a surface of the P well (36).

Abstract: The device hereof provides an integrated circuit resistor (34) comprising amorphous or noncrystalline semiconducting material. Further advantages can be gained in area by forming the noncrystalline semiconductor resistor in a non-planar fashion (i. e. with a vertical construction) wherein a first electrical contact is made to the resistor on its bottom surface and a second electrical contact is made to the resistor on its top surface.Other devices, systems and methods are also disclosed.

Abstract: An integrated analog to digital interface subsystem for imaging applications includes digital global and digital pixel by pixel offset correction and scaling. The integrated interface 2 includes 3 DAC's 2c1-2c3 that are used to do a rough offset cancellation on the three analog input signals (RGB) in the analog domain. A triple sample/hold circuit 2a samples the RGB signals simultaneously, multiplexes the data and passes the three signals on the ADC 2b sequentially (at about 3 times the data rate). The sample/hold circuit 2a has the capability to operate in fully differential as well as single ended input mode, and can perform correlated double sampling if needed. A high resolution ADC 2b converts the 3 multiplexed signals from simple/hold circuit 2a. A first digital offset correction circuit 2f restores the level of the RGB signals in the digital domain on a pixel by pixel basis.

Abstract: Built-In-Logic-Block-Observation registers BILBO are coupled to the output of a Control-Read-Only-Memory CROM in the write-state-machine of a flash EPROM. The Built-In-Logic-Block-Observation registers BILBO include master/slave latches M/SL, shadow latches SHL, and other logic circuitry that enable the various modes of operation required for pulse timing and for signature analysis. During operation a pre-defined FLASH command sequence requests a Control-Read-Only-Memory CROM signature analysis that executes a set of instructions causing the Built-In-Logic-Block-Observation registers BILBO to be placed in the Multiple-Input-Signature-Register Mode and that steps through the Control-Read-Only-Memory CROM until all valid addresses have been evaluated. The resultant Control-Read-Only-Memory CROM signature is then scanned out and verified. The invention eliminates the need for a separate stand-alone Linear-Feedback-Shift-Register LFSR used for pulse timing.

Abstract: A resonant tunneling diode stack used as a memory cell stack (X0-Xn) with sequential read out of bits of data cells (X1-Xn) by increasing ramp rates to transfer the stored bit to a lowest ramp rate cell (X0).

Abstract: An integrated circuit memory device (10) includes a large on-chip capacitor (12) that has a high voltage plate and a low voltage plate. The large on-chip capacitor (12) stores charge for a positive voltage supply (VPP) for the integrated circuit memory device (10). The high voltage plate of the large on-chip capacitor (12) is connected to a node (NODE 1) for distributing charge from the large on-chip capacitor. A load (16) is connected to the node (NODE 1) and consumes charge from the high voltage plate to power operations of the integrated circuit memory device (10). The load (16) includes a memory array comprising a plurality of memory cells. The low voltage plate of the large on-chip capacitor (12) is connected to a capacitive voltage reference which has high capacitance and has a voltage-level greater than ground potential and less than the positive voltage supply.

Abstract: This invention provides a cost-effective, easy-to-integrate Flash EPROM cell array. Starting with a substrate (31) of first conductivity-type, a first diffusion (30) of second conductivity-type forms the sources (11), and the connections between sources, of all of the memory cells (10) of the array. A second diffusion (32) of first conductivity-type forms the channel of at least one memory cell (10) in the array. A floating gate (13) and a control gate (14) of that memory cell (10) are located over, and insulated from, a junction of the first diffusion and the second diffusion. A third diffusion (33) of second conductivity-type is isolated in the second diffusion (32) to form the drain (12) of the memory cell (10). During operation, only positive voltages may be used for programming and erasing of the cells (10), thus eliminating the need for negative voltages and for triple-well diffusions. The cell array of this invention requires little or no current for Fowler-Nordheim erase operation.

Abstract: A data processing device includes a data processing core (43), a cache (33) connected to the core and having a cache width, and a bus (31) for receiving from an information source external to the data processing device a burst of information having a width which exceeds the cache width by a width difference. The cache is coupled to the bus to receive and store a first portion of the burst which is equal in width to the cache width. A storage circuit (35) is coupled to the bus to receive and store a second portion of the burst corresponding to the width difference, and the storage circuit has an output coupled to the core.

Abstract: This invention provides an improved porous structure for semiconductor devices and a process for making the same. This process may be applied to an existing porous structure 28, which may be deposited, for example, between patterned conductors 24. The method may comprise providing a substrate comprising a microelectronic circuit and a porous silica layer, the porous silica layer having an average pore diameter between 2 and 80 nm; and heating the substrate to one or more temperatures between 100 and 490 degrees C. in a substantially halogen-free atmosphere, whereby one or more dielectric properties of the porous dielectric are improved. In some embodiments, the atmosphere comprises a phenyl-containing atmosphere, such as hexaphenyldisilazane.

Abstract: Programmable time delay apparatus includes a plurality of similar components (10) which determine the total time delay of the apparatus. These components have gate units (31.sub.0 -31.sub.n,32.sub.0 -=.sub.n, 33.sub.0 -33.sub.n, 34.sub.0 -34.sub.n) coupled thereto which, in response to a control signal (b.sub.0 -b.sub.n) applied to each component, either electrically couples the component to the apparatus or electrically removes of the component from the apparatus. In a fist embodiment, the control signals (b.sub.0 -b.sub.n) place time delay components (10) in a series configuration, the total time delay being the sum of the time delays of each series-coupled component (10). In the second and third embodiment, the resistors (47.sub.0 -47.sub.n) and the capacitors (53.sub.0 -53.sub.n), respectively, are coupled in a capacitance charging circuit (47.sub.0 -47.sub.n, 43; 52, 53.sub.0 -53.sub.n), the coupled elements controlling the charging rate and, consequently, the time delay of the apparatus.

Abstract: An alignment system (30) is provided for use during the lithography process of producing multiple layer (24-26) integrated circuits. The location of each previous layer (24-26) in the integrated circuit is measured and evaluated with respect to each other and the wafer (14). The next layer is placed on the wafer (14) in a manner which optimizes its alignment relationship to each of the previous layers (24-26). Weighting factors are used to optimize alignment in multiple layer (24-26) integrated circuits.

Abstract: An on-chip voitage multiplier circuit, comprising N serially arranged stages wherein each stage includes a switch Tj (j=1 . . . N), having an upper pin and a lower pin, to the upper pin of which the lower pin of a capacitor Ci (i=1 . . . N) is serially connected, said capacitor also having a lower pin and an upper pin; the intermediate node between each switch Tj (j=1 . . . N) and each capacitor Ci (i=1 . . . N) is connected to the ground voltage Vss through a respective switch Si (i=1 . . . N) and the upper pin of each capacitor Ci (i=1 . . . N) is connected to the supply voltage Vdd through a switch Di (i=1 . . . N); and the lower pin of the switch (T11) of the first stage is directly connected to the supply voltage Vdd and the upper pin of the capacitor (CN) of the last stage is connected to the output pin through an additional switch (T(N+1)).

Abstract: In a dynamic random access memory, a sense amplifier has direct sense circuitry (MNRD, MNRD.sub.--, MNYSR, MNYSR.sub.--, MNYSW, MNYSR.sub.--) included therewith to minimize the effect of the parasitic impedances of the local INPUT/OUTPUT lines RES.sub.-- LIO, RES.sub.-- LIO.sub.--). The WRITE-ENABLE signal and the READ-ENABLE signal are each combined with the Y-SELECT signal to provide a Y-SELECT-READ and a Y-SELECT-WRITE signal. Each of these two signals, along with their complementary logic signals, control a transistor pair (MNYSR, MNYSR.sub.-- ; MNYSW, MNYSR.sub.--) in the direct sense circuitry, coupling the sense amplifier and the local INPUT/OUTPUT lines (RES.sub.-- LIO, RES.sub.-- LIO.sub.--). Because the original signal set had three enabling signals (along with their complements), the present implementation eliminates a transistor pair in the direct sense circuitry.

Abstract: A memory device implementing a Kanerva memory system is provided having an address space (12) and key addresses (14) therein. The key addresses (14) partition the address space (12) such that a hypersphere (17) defined by a radius of capture (16) for each key address (14) does not overlap a hypersphere (17) of any other key address (14). By such partitioning, at most one key address (14) can be activated during a read or write operation. Each key address (14) has an address decoder (24) determining if an input address falls within the hypersphere (17) of the key address (14). If so, the key address (14) is activated and a memory element (26) within each key address (14) stores the address data within multiple bit binary counters (28) by incrementing upon storing a binary 1 and decrementing upon storing a binary 0 during a write operation. In read mode, the contents of multiple bit binary counters (28) are transferred out of the memory device (10).

Abstract: A method for controlling oxygen-induced stacking faults (OISF) in a silicon crystal (12) grown according to the Czochralski silicon crystal growing technique includes the steps of forming a flared top portion (18) of the silicon crystal (12) to a predetermined diameter (20) and tapering (23) the silicon crystal (12) top portion (18) to produce a cylindrical portion (22) having a second predetermined diameter. The second predetermined diameter is smaller than the first predetermined diameter. Because of the inward taper (23) OISF concentrates in the flared top portion (18) of silicon crystal (12).

Abstract: In a dynamic random access memory unit, the voltage difference between bitline pairs, resulting from the transfer of charge between the bitline pair and a memory array (5.sub.L), is amplified by an associated sense amplifier unit (10.sub.L). A multiplicity of sense amplifier units (10.sub.1 -10.sub.M) are activated by a sense amplifier driver circuit. (16, 18, 15 and 17) in typical operation. During a first period of time, a first transistor circuit (15 and 17) of the sense amplifier driver unit capable of providing a limited amount of charging current, activates the sense amplifier units (10.sub.1 -10.sub.M). During a second period of time, the first transistor unit (15 and 17) and a second larger transistor unit (16, 18) activate the sense amplifier units. In order to provide a more effective activation during the first period, function of the first transistor circuit (15, 17) is performed by a plurality of transistor circuits (15.sub.1 -15.sub.L, 17.sub.1 -17.sub.

Abstract: A circuit (10, 40) and method for autotrim of an embedded threshold voltage reference bit are provided. A FAMOS cell (12, 42) in an integrated circuit chip provides the embedded threshold voltage reference bit. The FAMOS cell (12, 42) is first programmed to a threshold voltage above a desired threshold voltage. The FAMOS cell (12, 42) is then erased to lower the threshold voltage. After erasing, the FAMOS cell (12, 42) is tested to determine whether the threshold voltage is at a desired voltage level. The erasing and testing are accomplished automatically as an on-chip process in an integrated circuit chip. The testing can be based upon a comparison with an output of an internal reference circuit (50) that is responsive to the embedded threshold voltage reference bit. The testing can also be based upon a comparison to an external voltage input or an internal voltage reference.

Abstract: An output buffer with a slew rate that is load independent is comprised of an output buffer (14) that is connected to an output terminal (12). The output buffer (14) is controlled such that it can drive a load (18) with different drive levels by changing the transconductance internal thereto. The transition on the input to the buffer (14) is passed through an intrinsic delay block (34) and variable delay block (40) to provide a delay signal on a node (42). A first phase detector latch (50) with a first threshold voltage compares this transition with the transition on the output terminal (12). A second phase detector latch (60) with a second threshold voltage, also compares this delayed transition with that on the output terminal (12). If both of the latches (50) and (60) indicate that the delayed transition occurred after the transition on the output terminal (12), a control signal on a line (78) is changed by incrementing a counter (74). This will increase the drive to a load (18).