Abstract: A composite bond pad that is resistant to external forces that may be applied during probing or packaging operations is presented. The composite bond pad includes a non-self-passivating conductive bond pad (134) that is formed over a semiconductor substrate (100). A dielectric layer (136) is then formed over the conductive bond pad (134). Portions of the dielectric layer (136) are removed such that the dielectric layer (136) becomes perforated and a portion of the conductive bond pad (134) is exposed. Remaining portions of the dielectric layer (136) form support structures (138) that overlie that bond pad. A self-passivating conductive capping layer (204) is then formed overlying the bond pad structure, where the perforations in the dielectric layer (136) allow for electrical contact between the capping layer (204) and the exposed portions of the underlying bond pad (134).

Abstract: A passive integrated component (10) is formed overlying a semiconductor substrate by etching a composite conductive layer using a solution of sodium persulfate or ceric ammonium nitrate to remove a lower portion of the composite copper layer (64) exposed by an upper portion of the composite copper layer (74, 76, 78) to expose an underlying surface (62).

Abstract: An etch stop layer (12) is formed over a semiconductor substrate (10). An epitaxial layer (14) is formed overlying the etch stop layer (12). The combination of the epitaxial layer (14), etch stop layer (12), and semiconductor substrate (10) form a composite substrate (16). The composite substrate (16) is processed to fabricate a semiconductor device (21) over the epitaxial layer (14). Then the composite substrate (16) is mounted to a wafer carrier (32) to expose the semiconductor substrate (10) and the semiconductor substrate (10) is removed to substantially define a semiconductor device substrate (50) that comprises the epitaxial layer (14).

Abstract: An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

Abstract: In accordance with one embodiment of the present invention, a semiconductor device underbump metallurgy (414) is formed over a semiconductor bond pad (128), wherein the underbump metallurgy (414) comprises a chromium, copper, and nickel phased-region (404), and wherein the presence of nickel in the phased-region (404) inhibits conversion of tin from the solder bump and other tin sources from forming spallable Cu6Sn5 copper-tin intermetallics.

Abstract: In accordance with one embodiment, a stress buffer (40) is formed between a power metal structure (90) and passivation layer (30). The stress buffer (40) reduces the effects of stress imparted upon the passivation layer (30) by the power metal structure (90). In accordance with an alternative embodiment, a power metal structure (130A) is partitioned into segments (1091), whereby electrical continuity is maintained between the segments (1090) by remaining portions of a seed layer (1052) and adhesion/barrier layer (1050). The individual segments (1090) impart a lower peak stress than a comparably sized continuous power metal structure (9).

Abstract: A semiconductor device and method of fabrication are disclosed. The device includes a first trench isolation region having an allowable tiling area and a second trench isolation region having an allowable tiling area, wherein the second trench isolation region is doped differently from the first trench isolation region. First tile structures disposed within first trench isolation region have a first set of design parameters while second tile structures disposed within the second trench isolation region have a second set of design parameters. At least one of the first set of design parameters is different from a corresponding design parameter in the second set of design parameters. The corresponding design parameters may include the density, size, pitch, shape, exclusion distance, minimum width, minimum length, and minimum area. The first trench isolation region may be doped with a first-type dopant and the second trench isolation region may be undoped or doped with an opposite second-type dopant.

Abstract: A method and apparatus for decreasing contact resistance between a ohmic contact (120) and a semiconductor material (106) are disclosed. Increased contact resistance, which occurs as a result of encroachment of the ohmic contact (120) into the semiconductor material (106) is compensated for by notching edges of the ohmic contact (1210) to increase the effective surface area between abutting surfaces of the ohmic contact (120) and semiconductor material (106). The increase in surface area increases the effective transfer length of the contact, which correspondingly reduces contact resistance and improves device performance.

Abstract: A wafer carrier (300) for a CMP tool is adjustable to provide center fast to edge fast material removal from a semiconductor wafer. The wafer carrier (300) holds the semiconductor wafer without vacuum. The semiconductor wafer is held by a carrier ring (308). An elastically flexed wafer support structure (318) is a support surface for the semiconductor wafer. Elastically flexed wafer support structure (318) can be bowed outward or bowed inward in an infinite number of different contours. The semiconductor wafer conforms to the contour of the elastically flexed wafer support structure (318) when a down force is applied to the wafer carrier (300) during a polishing process. Changing the contour is used to produce different material removal rates across the radius of the semiconductor wafer to increase wafer planarity in a polishing process.

Abstract: Techniques for forming gate dielectric layers (702) overlying amorphous substrate materials are presented. In addition, techniques for low temperature processing operations that allow for the use of amorphous silicon in doping operations are presented. The amorphous silicon regions (604, 606) are formed prior to formation of structures included in the gate structure (804) of the semiconductor device, where the gate structures (804) are preferably formed using low temperature operations that allow the amorphous silicon regions (604, 606) to remain in an amorphous state. Source/drain regions (1004, 1006) are formed in the amorphous silicon regions (604, 606), and then the substrate is annealed to recrystallize the amorphous regions.

Abstract: A semiconductor device (10) having a stacked-gate buffer (30) wherein the stacked-gate buffer (30) has a substrate (65) and a top substrate region (70) both with the same first conductivity type. The buffer (30) also has two transistors (95.105), each with a current carrying electrode and a control electrode (90, 100). A deep doped region (120) lies between the first (90) and second (100) control electrodes where the deep doped region (120) is another current carrying electrode for the first transistor (95) and another current carrying electrode for the second transistor (105) and the deep doped region (120) has a second conductivity that is opposite the first conductivity type. A deeper doped region (80) is also part of the stacked-gate buffer which has a second conductivity type and lies between the first (90) and second (100) control electrodes and is deeper than the deep doped region (120). A method of forming the device is also provided herein.

Abstract: In one embodiment, a first dielectric film (24), and a second dielectric film (32) are formed over a substrate (10). The substrate is cured to at least partially change a property of the second dielectric film thereby forming an intermediate etch stop (46). A third dielectric film (42) is formed over the substrate (10). The substrate (10) is then etched to remove portions of the first dielectric film (24) and portions of the third dielectric film (42) using the intermediate etch stop (46) to form a portion of an interconnect opening (103). In an alternative embodiment, a resist layer (92), and portions of an interlevel dielectric layer (50) are etched. Upon completion of the step of etching, the photoresist layer (92) and portions of the interlevel dielectric layer (50) are completely removed.

Abstract: A self-aligned magnetic clad bit line structure (274) for a magnetic memory element (240a) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure (274) extends within a trench (258) and includes a conductive material (250), magnetic cladding sidewalls (262) and a magnetic cladding cap (252). The magnetic cladding sidewalls (262) at least partially surround the conductive material (264) and the magnetic cladding cap (252) is substantially recessed within the trench with respect to the top of the trench.

Abstract: A silicon-on-insulator substrate and its method of formation are disclosed. In another embodiment, a method for forming a high-k gate dielectric is disclosed. The silicon-on-insulator substrate is prepared by forming a lattice matched dielectric layer (20) over a semiconductor substrate (10). A thermodynamically stable dielectric layer (22) is then formed over the lattice matched dielectric layer (20). A semiconductor layer (30) is then formed over the thermodynamically stable dielectric layer (22). Formation of the high-k gate dielectric includes the processing steps used to form the silicon-on-insulator substrate and additionally includes bonding a second semiconductor substrate (50) to the semiconductor layer (30). The first semiconductor substrate (10) is then removed to expose the lattice matched dielectric layer (20). This results in a silicon substrate that has a layer of high-k dielectric material that can be used as the gate dielectric for integrated circuits formed on the substrate.

Abstract: A metal-organic precursor suitable for use in a chemical vapor deposition formation of dielectric layer is disclosed. The precursor comprises a moiety that includes a first metal atom, an oxygen atom, and a nitrogen atom. The oxygen atom is chemically bonded to the metal atom and to the nitrogen atom. The first metal atom may be a Group III, Group IV, or Group V transition metals such as yttrium, lanthanum, titanium, zirconium, hafnium, niobium, and tantalum or another metal such as aluminum. The precursor may include one or more alkoxy groups bonded to the first metal atom. The precursor may be characterized as a M(OCR3)X−Y−Z(ONR2)Y(OSiR3)Z molecule where Y is an integer from 1 to (X−1), Z is an integer from 0 to X−1, X is an integer from 3 to 5 depending upon the valency of M and (Y+Z) is less than or equal to X. In one embodiment the precursor further includes one or more siloxy or alkyl siloxy groups bonded to the first metal atom.

Abstract: An electroplating system (30) and process makes electrical current density across, a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

Abstract: A semiconductor device and its method of formation are disclosed wherein a surface of a semiconductor substrate is planarized to form an interconnect (1244) within a dielectric layer (1243). The top surface of the dielectric layer is then recessed with respect to a top surface of the interconnect to form a step (201). An opaque film (301) is then deposited over the surface of the semiconductor substrate. The opaque film (301) is lithographically patterned and etched, wherein an alignment of the patterning layer (401) is accomplished using topographically discernable features (303) that are formed in the opaque film (301) in regions where the step (201) between the interconnect (1244) and dielectric layer (1243) is produced.

Abstract: A method and an apparatus for forming a layer on a substrate are disclosed. In accordance with one embodiment, a substrate (901) is placed into a chamber (30) that includes a coil (16) and a shield (14) wherein the coil and the shield are electrically isolated by an isolation/support member (32) having a first surface (321) that is substantially contiguous with a surface of the coil and having a second surface (322) that is substantially contiguous with a surface of the shield. A layer (1002, 1102) is then deposited onto the substrate (901).

Abstract: A method for forming a semiconductor device is disclosed in which a fluorinated silicon dioxide layer is formed over a semiconductor substrate. A first undoped silicon dioxide layer, with a thickness preferably less than approximately 50 nanometers, is then formed on the fluorinated silicon dioxide layer with a PECVD process wherein a power ratio of a high frequency power source of the PECVD reactor to a low frequency power source is preferably in a range of approximately 0.2:1 to 0.4:1. In one embodiment, a second undoped silicon dioxide layer may be formed prior to forming the fluorinated silicon layer. The second undoped silicon dioxide, the fluorinated silicon dioxide layer, and the first undoped silicon dioxide layer may be formed sequentially in the same plasma enhanced chemical vapor deposition process chamber during a single chamber evacuation cycle. The first undoped silicon dioxide layer is preferably characterized as having a refractive index greater than approximately 1.460.

Abstract: A method for forming an improved copper inlaid interconnect (FIG. 11) begins by performing an RF preclean operation (408) on the inlaid structure in a chamber (10). The RF preclean rounds corners (210a and 206a) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces (202a). A tantalum barrier (220) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer (220), a copper seed layer (222) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp (85) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.