Abstract: A method for forming an improved copper inlaid interconnect (FIG. 11) begins by performing an RF preclean operation (408) on the inlaid structure in a chamber (10). The RF preclean rounds corners (210a and 206a) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces (202a). A tantalum barrier (220) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer (220), a copper seed layer (222) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp (85) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.

Abstract: A semiconductor device substrate (600, 900) includes a semiconductor device (310, 314, 405, 424, 506, 912, 914, 918) and an alignment structure (508, 902) lying near the semiconductor device. The substrate (600, 900) includes a reflective layer (506, 510) and an antireflective layer (316, 926). The antireflective layer (316, 926) has a positional relationship with respect to the reflective layer (506, 510). The positional relationship is either such that the antireflective layer (316, 926) overlies all the reflective layer (506, 510) or such that none of the antireflective layer (316, 926) overlies the reflective layer (506, 510). The alignment structure (508, 902) includes an alignment feature (512), such as an alignment key.

Abstract: A lithographic mask (FIG. 9 or FIG. 10) that is primarily used for SCALPEL processing has a substrate (100). Layers (102, 104, 106, 108, 110, and 112) are formed and selectively patterned and etched to form E-beam exposure windows (118) and skirt regions (120) framing the windows (118). The skirt regions (120) and some portions of the patterned features (124) within the window (118) are formed having thicker/thinner regions of material or formed of different material whereby different regions of the mask (FIG. 9) scatter energy to differing degrees. The different scattering regions on the mask allow SCALPEL patterns to be formed on the wafer with improved critical dimension (CD) control, reduced aberrant feature formation, and improved yield.

Abstract: A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.

Abstract: A semiconductor device and its method of fabrication are disclosed. The method includes forming a first well region in a semiconductor substrate. The semiconductor substrate includes a first doped region below the first well region. The first well region and the first doped region are doped with a first type dopant and the first well region is electrically connected to the first doped region. An isolation region is formed between the first well region and the first doped region. The isolation region is electrically connected to a second well region. The isolation region and the second well region are doped with a second dopant type The second dopant type is opposite the first dopant type. In one embodiment, the first type dopant includes a p-type dopant, and the second type dopant includes an n-type dopant. The method may further include, forming a second doped region within the first well region and below the isolation region.

Abstract: A semiconductor device includes a non-volatile memory, such as an electrically erasable programmable read only memory (EEPROM) array of memory cells. The memory is arranged as an array of cells in rows and columns. P-well regions of the array are spaced apart and electrically isolated by shallow trench features. The cells of each column are positioned within a respective isolated p-well region. Control gates of sequentially corresponding memory cells in columns of the array are electrically coupled by common wordlines. Bitlines electrically couple drain regions of each memory cell in the respective columns of the memory cell array. Source lines electrically couple source regions of each memory cell in the respective columns of the array. The source lines and at least one memory cell in each column of the array are electrically coupled to the p-well region corresponding to the column of the source line and cell.

Abstract: Testing is performed on a semiconductor die (50) having a plurality of protruding electrical contacts (52) formed thereon. The test method uses a carrier (100) having a plurality of wells (110) formed in a dielectric layer (118) thereon. At least a portion of the protruding electrical contacts (52) is inserted into a corresponding portion of the plurality of wells (110) in order to make electrical connections between the semiconductor die (50) and the carrier (100) with minimal damage to the protruding electrical contacts (52). Testing (e.g. functional testing, burn-in testing, full-speed testing) of the semiconductor die (50) may then be performed using the electrical connections. Once testing of the semiconductor die (50) is completed, the semiconductor die (50) is removed from the carrier (100) and the carrier (100) may be reused for testing a different semiconductor die.

Abstract: A memory device is presented that utilizes isolated storage elements (200) in a floating gate structure, where tunneling holes (404) are used to program the device and tunneling electrons (504) are used to erase the device. Formation of such a device includes forming a thin tunnel dielectric layer (102) that may be less than 3.5 nanometers. When the control gate electrode (204) of the memory device is negatively biased, the thinner tunnel dielectric (102) allows holes to migrate through the tunnel dielectric to positively charge the isolated storage elements (200). When the device is to be erased, the control gate electrode (204) is positively biased, and rather than forcing the holes back across the tunnel dielectric, electrons present in the channel (402) are pulled through the tunnel dielectric where they recombine with the holes in the floating gate such that the stored positive charge is substantially neutralized.

Abstract: A method of forming a metal colloid comprising a plurality of particles, each particle comprising a core of a metal, is described. The method comprises the steps of providing an organometallic precursor comprising the metal, combining the organometallic precursor and a solvent, which comprises water molecules, heating the combination of organometallic precursor and solvent so that the organometallic precursor decomposes to form a solution including the metal colloid and by-products, and removing the by-products to provide the metal colloid.

Abstract: An integrated circuit substrate (10) is uniformly coated with a defect free layer of material (18), while minimizing the volume of material (18) dispensed on to the integrated circuit substrate (10). In one embodiment a first predetermined quantity of material (18) is dispensed on to the integrated circuit substrate (10) while the integrated circuit substrate (10) is not spinning. After the first predetermined quantity of material (18) is dispensed the integrated circuit substrate (10) is radially accelerated to a first predetermined spin speed. A second predetermined quantity of the material (18) is then dispensed on to the first predetermined quantity of material (18), while the integrated circuit substrate (10) is spinning. After the second predetermined quantity of material (18) is dispensed the integrated circuit substrate (10) is radially accelerated to a second predetermined spin speed.

Abstract: A refractory Metal Nitride and a refractory metal Silicon Nitride layer (64) can be formed using metal organic chemical deposition. More specifically, tantalum nitride (TaN) (64) can be formed by a Chemical Vapor Deposition (CVD) using Ethyltrikis (Diethylamido) Tantalum (ETDET) and ammonia (NH3). By the inclusion of silane (SiH4), tantalum silicon nitride (TaSiN) (64) layer can also be formed. Both of these layers can be formed at wafer temperatures lower than approximately 400° C. with relatively small amounts of carbon (C) within the film. Therefore, the embodiments of the present invention can be used to form tantalum nitride (TaN) or tantalum silicon nitride (TaSiN) (64) that is relatively conformal and has reasonably good diffusion barrier properties.

Abstract: Semiconductor devices and conductive structures can be formed having a metallic layer. In one embodiment, a semiconductor device includes an amorphous metallic layer (22) and a crystalline metallic layer (42). The amorphous metallic layer (22) helps to reduce the likelihood of penetration of contaminants through the amorphous metallic layer (22). A more conductive crystalline metallic layer (42) can be formed on the amorphous metallic layer (22) to help keep resistivity relatively low. When forming a conductive structure, a metal-containing gas and a scavenger gas flow simultaneously during at least one point in time. The conductive structure may be part of a gate electrode.

Abstract: In accordance with embodiments of the present invention a trench-level dielectric film (26) and a via-level dielectric film (24) are formed overlying a semiconductor device substrate (10). A via opening (42) is etched in the trench-level dielectric film with a first etch chemistry that has a higher etch selectivity to the trench-level dielectric film (26) than to the via-level dielectric film (24). A trench opening (54) is patterned in a photoresist layer (52) overlying the trench-level dielectric film (26). The via-level dielectric film (24) is etched with a second etch chemistry to extend the via opening (42) into the via-level dielectric film (24). The trench-level dielectric film (26) is etched to form a trench opening.

Abstract: A method for forming void free tungsten plug contacts (56a-56c) begins by etching a contact opening (55a-55c) using a C2F6 and CHF3 chemistry. The etch chemistry is then changed to an O2 and CH3F chemistry in order to insitu remove the contact photoresist while tapering an upper portion of the contact opening. A tungsten deposition process is then performed whereby the tapered portion of the contact reduces the effects of nonconformal and step-coverage-inconsistent tungsten deposition wherein voids in the contact are either substantially reduced or totally avoided within the contact structure. The reduction of or total elimination of voids (22) within the tungsten contact will increase yield, increase reliability, and reduce electromigration failures within integrated circuit devices.

Abstract: An apparatus and method is disclosed for a semiconductor wafer front side pressure testing system (200, 300, 400). Negative or positive pressure is applied to the top portion of a semiconductor wafer (216, 316) mounted on a support structure or wafer chuck (222, 322, 422). In one embodiment, bellows (232) coupled to the wafer chuck (222, 322, 422) and a platen (218, 318, 418) located above the semiconductor wafer (216, 316) provides a sealed atmosphere above the semiconductor wafer (216, 316) to permit negative or positive pressure to be introduced into this sealed atmosphere. In another embodiment, a seal is provided by a wall portion (421) connected to the chuck (422) contacting a gasket (419) located beneath the platen (418).

Abstract: A method of forming a hard mask for use in the formation of a refractory radiation mask including providing a membrane structure, forming a radiation absorbing layer to be patterned on the membrane structure, forming a hard mask layer on the surface of the membrane structure, the hard mask layer including a material system having a nominally zero stress and therefore reduced distortion of the membrane structure, and patterning the hard mask layer.

Abstract: In accordance with one embodiment of the present invention, a method is disclosed for forming a semiconductor device having an isolation region (601). A dielectric layer (108) is deposited and etched to form isolation regions (102, 605) having top portions that are narrower than their bottom portions, thereby a tapered isolation region is formed. Active regions (601, 603) are formed using an epitaxial process in the regions between the isolation regions. The resulting active regions (601, 603) have a greater amount of surface area near a top portion, than near a bottom portion. Transistors (721, 723) having opposite polarities are formed within the active areas.

Abstract: A method for fabricating a patterning mask is disclosed in which a membrane layer is deposited on a first surface of a substrate. Patterned and unpatterned portions of the substrate are then defined on a second surface of the substrate. A majority of the thickness of substrate in the unpatterned portions is then dry etched to partially define a strut having sidewalls that are substantially perpendicular to the first surface. Wet etching is then performed to etch through the remaining thickness of the substrate to expose the bottom surface of the membrane layer and completely define the strut. Scattering elements may then be formed over the membrane layer. In one embodiment, the substrate is silicon and has a (110) orientation and an edge of the silicon struts is aligned to a {111} plane. In another embodiment, an edge of the silicon struts is aligned to a {221} plane.

Abstract: A method of operating a semiconductor device that includes a first memory cell with discontinuous storage elements or dots (108) in lieu of a conventional floating gate can be programmed to at least one of three different states. The different states are possible because the read current for the memory cell is different when the dots are programmed near the source region or near the drain region. Embodiments may use two different potentials for power supplies or three different potentials. The two-potential embodiment simplifies the design, whereas the three-potential embodiment has a reduced risk of disturb problems in adjacent unselected memory cells (100B, 100C, and 100D).

Abstract: A memory cell (101), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (101) comprises a first and second current carrying electrode (12) a control electrode (19), and doped discontinuous storage elements (17). In accordance with an alternative embodiment, memory cell programming is accomplished by removing or adding an average of approximately at least a first charge (30, 62, 64), which can be electron(s) or hole(s) from each of the doped discontinuous storage elements (17).