Abstract: A nonresilient rigid test probe arrangement which is designed for testing the integrity of silicon semiconductor device wafers or chips, and which eliminates pliant conditions encountered by current text fixtures, which are adverse to the attainment of satisfactory test results with rigid probes. The test system interface assembly includes a rigid ceramic substrate which forms a pedestal over which the rigid probe makes electrical contact. A PC board is located on the opposite side of the ceramic substrate. A clamp ring retains the PC board to a test head system with mating precision reference surfaces formed therebetween. Pogo pin connectors extend between the PC board and the test head system. A stiffening element having a control aperture is bolted through the PC board to the clamp ring, all of which form a rigid test probe arrangement.

Abstract: Redundant chip sections held in standby are substituted for chip sections that are at risk of over heating based on certain sensor signals. When these signals are received operations of the chip section at risk IS transferred to a redundant chip section and the chip section at risk is shut down. After the original chip section has cooled, it becomes available as a replacement chip section itself. The sensor signals may be based on temperature values, elapsed operation time, and number or rate of operations within a chip section.

Abstract: A method of forming a semiconductor device having aluminum lines therein, wherein the occurrence of lateral extrusions and voids are reduced. The method comprises the formation of a metal stack on a surface of the substrate, wherein the aluminum layer of the metal stack is deposited under controlled conditions; etching the metal lines in the metal stack; and exposing the substrate to a subsequent anneal.

Abstract: A monolithic probe having an integral fine probe point, pressure spring, conductive line, and connector for contacting semiconductor devices to be tested and a method of construction of said probe is described. Integration of a serpentine spring into the probe body reduces breakage and improves contact reliability. Standard, coaxial, triaxial, and Kelvin probes are described. The methods of construction described utilize standard semiconductor processes. The probes may be fabricated to very small dimensions.

Abstract: The leakage current on a semiconductor is reduced while the semiconductor is in a sleep mode. This is accomplished by (1) placing the semiconductor in the sleep mode; (2) providing the semiconductor an internal supply voltage derived from an external supply voltage applied to the semiconductor chip (where the internal supply voltage is less in quantity than the external supply voltage); and (3) reducing the internal supply voltage when the semiconductor enters the sleep mode from an activated mode and returning the internal supply voltage to an activated mode level when the semiconductor returns to the activated mode. The reducing step includes supplying the external supply voltage to a reference circuit which outputs therefrom a reference voltage; and supplying the reference voltage to a regulator, where the regulator attempts to match the reference voltage and outputs therefrom the internal supply voltage.

Abstract: A high performance memory array architecture is provided to minimize the delays within each array. The architecture of the array equalizes the access time to all memory elements by optimizing the positioning of the subarrays with respect to buffering and rebuffering elements used in the array which cause delays.

Abstract: A first one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer beneath a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench. A second one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer formed in a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer.

Abstract: Method and system for real-time in-situ interactive supervision of a step performed in a tool during semiconductor wafer fabrication process. The system includes a tool and the computer attached thereto, an end point detection controller, a database and a supervisor to supervise the whole wafer processing for that step. The controller is used to monitor a key process parameter of the step and is adapted to perform in-situ measurements. The database contains the evolution of said process parameter in normal operating conditions and in all the identified deviations. It further contains the history of the wafer until this step and a reference to the batch and process names for this step and the wafer identification number. At the end of the step, the important process parameters and any alert code are stored in the database to up-date the wafer history. This technique allows a total clusterized wafer fabrication process and prevents wafer rejection.

Abstract: An integrated circuit assembly has pads of a chip electrically connected to pads of a substrate with rolling metal balls. A pliable material bonds the balls in movable contact with pads of the chip and substrate. Because the balls are relatively free to move, thermal expansion differences that would ordinarily cause enormous stresses in the attached joints of the prior art, simply cause rolling of the balls of the present invention, avoiding thermal stress altogether. Reliability of the connections is substantially improved as compared with C4 solder bumps, and chips can be safely directly mounted to such substrates as PC boards, despite substantial thermal mismatch.

Abstract: An apparatus and method are provided that preserve data coherency within a DDR SRAM without sacrificing SRAM performance. The presence of a read-following-double-write (RFDW) condition is detected and data is prevented from being output from the SRAM following detection of the RFDW condition until coherent data is available. To detect an RFDW condition, preferably a double write signal is detected during a double write operation, and the double write signal is latched. A read signal also is detected during a read operation and the latched double write signal is compared to the read signal. If both the latched double write signal and the read signal are in a logic state that indicates that each is being performed, the RFDW condition is deemed detected. To prevent data from being pre-maturely output from the SRAM, the off chip driver circuitry of the SRAM preferably is maintained in a tri-state condition and data within a write buffer of the SRAM preferably is blocked until coherent data is available.

Abstract: A method and apparatus for chemical mechanical polishing a semiconductor wafer by providing a novel high pressure mixture of gas and liquid in a pulsation mode for eliminating residual slurry, by-products, and slurry abrasive particles on or in the polishing pad.

Abstract: The disclosed invention relates generally to electronic data storage systems that access data storage memory modules via a data bus comprised of multiple data query lines and, more particularly, to an electronic data storage system provided with a data bus that can be selectively provided with terminations thereby permitting the data storage memory to use either modules that require that the data query lines be open-ended, i.e., without terminations or modules that require that the data bus be terminated and to a method for operating such a system. The present invention is particularly directed to a single memory system that can accommodate either 3.3V DIMMs or DDR DIMMs. This is especially accomplished by providing the processor circuit, used in memory storage systems, with both (3.

Abstract: Methods and apparatus for blowing and sensing antifuses are provided. Specifically, in a first aspect, a method is provided for changing the state of one of a plurality of antifuses by selecting one of the bank of antifuses and applying a high voltage to change the state of the selected antifuse. In second and third aspects, apparatus are provided for performing the method of the first aspect. In a fourth aspect, a method is provided for boosting a voltage that includes the steps of generating a first voltage within a first stage storage mechanism of a first stage voltage booster circuit, generating a second voltage equaling about twice the first voltage within a first and a second, second stage storage mechanism of a second stage voltage booster circuit, and generating about thrice the first voltage based on the second voltage of the second stage voltage booster circuit. In a fifth aspect, apparatus are provided for performing the method of the fourth aspect.

Abstract: In many DRAM (Dynamic Random Access Memory) architectures, a sense amplifier detects and amplifies a small voltage differential between complementary bitline pairs to read from/write to a DRAM memory cell. The access speed of the DRAM is dependent on the speed of the transition, due to this amplification, of the bitline pairs from an equalized, pre-charged voltage level to final (within a given sensing cycle) high and low levels. The transition speed of the bitline pairs can be increased by providing a higher overdrive voltage to the sense amplifier. As DRAM technologies are scaled successively smaller, the overdrive voltage must be controlled to avoid compromising the reliability of the DRAM. Accordingly, the present invention relates to a DRAM circuit which provides a transiently higher overdrive voltage only during sensing. The overdrive is provided by a pre-charged capacitive source utilizing the circuit's natural capacitance.

Abstract: A multilayered quantum conducting barrier (MQCB) structure formed on two semiconductor regions having a different crystalline nature and a thin layer of an insulating material sandwiched between said semiconductor regions. An undoped amorphous silicon layer continuously coats these two semiconductor regions and insulating layer. The surface of the undoped amorphous silicon layer is nitridized to produce a superficial film of a nitride based material to form the desired quantum conducting barrier (QCB). A stack consisting of at least one dual layer comprised of a bottom undoped amorphous silicon layer and a top dopant monolayer is formed on said undoped amorphous silicon layer. After thermal processing, the MQCB structure operates as a strap allowing an electrical continuity between these semiconductor regions through the QCB by a quantum mechanical effect.

Abstract: There is disclosed a method of forming a buried strap (BS) and its quantum conducting barrier (QCB) in a structure wherein a doped polycrystalline silicon region is exposed at the bottom of a recess and separated from a monocrystalline region of a silicon substrate by a region of an insulating material. First, a thin continuous layer of undoped amorphous silicon is deposited by LPCVD to coat said regions. The surface of this layer is nitridized to produce a Si3N4 QCB film. Now, at least one dual layer comprised of an undoped amorphous silicon layer and a dopant monolayer is deposited onto the structure by LPCVD. The recess is filled with undoped amorphous silicon to terminate the buried strap and its QCB. Finally, the structure is heated to activate the dopants in the buried strap to allow an electrical continuity between said polycrystalline and monocrystalline regions through the QCB by a quantum mechanical effect. All these steps are performed in situ in the same LPCVD tool.

Abstract: The disclosed invention provides a reduction of voltage noise or bounce in logic chips and does so in a practical way without requiting additional circuit elements that impact on circuit performance or speed. Broadly this reduction in voltage bounce is achieved by forcing the unused Input/Output (I/O) circuits, i.e., those chips not being activated, to serve as alterative paths to the voltage power supply used by the switching circuits. More particularly this is accomplished this by grouping the I/O points on the chips into logical, functional units such as data buses, control lines, the I/O points on switched circuits, i.e., those switched at high frequency and the I/O points on static circuits, i.e., non-switched and interconnecting and using the I/O points on the static circuits and the power supply drives coupled thereto as alternate pats to the power supply used by the switched circuits.

Abstract: There is disclosed an improved method of forming the spacer which isolates the gate conductor from the metal contact with the diffusion (source/drain) region of each array transfer transistor for all memory cells of a DRAM chip. According to the method there is provided a structure consisting of a silicon substrate having a diffusion region formed therein and gate conductor (GC) lines formed thereon. Then, an oxynitride layer and a silicon nitride (Si3N4) layer are conformally deposited in sequence onto the structure by LPCVD in the same tool for total clusterization. Next, the structure is anisotropically dry etched with a chemistry that is Si3N4/oxynitride selective to expose the oxynitride layer between the GC lines and the upper portion thereof in a one step process to form the Si3N4 spacers.

Abstract: A method for accessing to a DRAM and a DRAM controller of the same, which enables a high speed DRAM access and a DRAM controller. Provided is an accessing method to a DRAM, which comprises the steps of detecting an access type to the DRAM; and changing an access mode depending on the detected access type. Furthermore, provided is an accessing method to a DRAM which comprises the steps of detecting whether a currently accessed row address and an address lastly accessed; and changing an access mode depending on an existence of the coincidence of the detected row addresses.

Abstract: A structure and method for testing multi-port SRAM cells includes a test controller connected to at least one multi-port SRAM cell (the test controller is adapted to store a pattern into the multi-port SRAM cell and generate a stability test restore clamp), a read/write controller connected to the multi-port SRAM cell (the read/write controller is adapted to simultaneously activate a plurality of wordline ports on the multi-port SRAM cell while the stability test restore clamp is enabled), and a timing control circuit connected to the read/write controller. The timing control circuit is adapted to vary an activation time of the wordline ports. The read/write controller reads from the multi-port SRAM after the stability test restore clamp is deactivated. The read/write controller activates the wordline ports for each multi-port SRAM cell in an array sequentially while all bitlines in the array are held on by the stability test restore clamp.