Abstract: The leakage current on a semiconductor is reduced while the semiconductor is in a sleep mode. This is accomplished by (1) placing the semiconductor in the sleep mode; (2) providing the semiconductor an internal supply voltage derived from an external supply voltage applied to the semiconductor chip (where the internal supply voltage is less in quantity than the external supply voltage); and (3) reducing the internal supply voltage when the semiconductor enters the sleep mode from an activated mode and returning the internal supply voltage to an activated mode level when the semiconductor returns to the activated mode. The reducing step includes supplying the external supply voltage to a reference circuit which outputs therefrom a reference voltage; and supplying the reference voltage to a regulator, where the regulator attempts to match the reference voltage and outputs therefrom the internal supply voltage.

Abstract: A system and method that integrates film thickness measurements with a chemical-mechanical polishing (CMP) spin-dry tool. By doing so, each wafer can be measured as it comes out of the previous CMP process. Thickness measurement feedback is provided, which controls processing of the wafer and also monitor operational status of a CMP polishing unit prior to completion of the wafer being polished, resulting in significant cost and cycle time reduction through the elimination of tool infrastructure and wafer handling by assuring proper tolerances of the CMP polishing unit are maintained.

Abstract: To provide an improved memory in which code or data can be read out in the original order even when it is successively accessed by a processor of a successive type according to addressing in a grey code system and a method of storing code/data in such memory. Code/data addressed in the original binary code system are stored in a memory in the form in which the original order and continuity are not lost even after the addresses are converted to a grey code system. Accordingly, a processor of successive type can read out code or data in the original order by consecutively outputting addresses according to a grey code address system. The power consumption of the address generator can be reduced in accessing to consecutive addresses by having addresses of the memory space expressed in a grey code.

Abstract: An integrated distribution wiring system for a semiconductor substrate having a number of devices. The distribution system includes additional stripes which are arranged parallel to existing rails carrying power or signals to the devices. These stripes being separable from the rails may be used to make engineering changes such as repairs or modifications of the circuits in the devices or characterizing or diagnosing the devices.

Abstract: Semiconductor materials are prepared by CMP with a first rough polishing step using an acidic slurry followed by cleaning a the pad and wafer separately. After cleaning a second polishing step with a basic slurry is used which buffs the wafer. Finally the pad and wafer are rinsed while a low pressure is applied to complete the process.

Abstract: A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, a synchronous static randomly addressable row register, a select logic gating circuit, and mode register for programming of the cached SDRAM to operate in a Write Transfer mode corresponding to a Normal Operation mode of a standard SDRAM during a Write cycle, and to operate in a No Write Transfer mode according to an alternate operation mode during a Write cycle, thereby operating under a first and a second caching policy, respectively. The SDRAM includes a row decoder for selecting a row of data in a memory bank array, sense amplifiers for latching the row of data selected by the row decoder, and a synchronous column selector for selecting a desired column of the row of data.

Abstract: A carrier rinse unit comprising a plurality of nozzles prepositioned to eject a cleaning fluid against a surface of a wafer while the wafer is rotated within a wafer carrier. The prepositioned nozzles may be angled to spray a leading edge, a trailing edge, an outer edge of the wafer, or any desired point on the surface of the wafer.

Abstract: A variable digital delay line with an insertion delay as low as a single delay element yet capable of providing a large programmable delay with a small simple control mechanism. A loop connects an input to an output through selectable first delay elements such as 2:1 muxes and selectable second delay elements such as pairs of inverters by way of a plurality of intermediate nodes having a tap. A plurality of sneak paths are available wherein the loop by passes a remainder of first delay elements and/or second delay elements by way of the taps at the intermediate nodes.

Abstract: An improved method of forming the buried plate regions in deep trench capacitors used in DRAM memory semiconductor circuits in which the polymer used in the deep trench is etched down to the desired depth in a reactive ion etch tool using an O2/CF4 chemistry. Since optical/interferometric etch end-point detection system can be used to monitor the etch back step in its totality, the quantity of the polymer remaining in deep trenches can be very accurately controlled, which in turn will produce a well controlled buried plate region during the out-diffusion step of the arsenic dopant contained in the arsenic doped silicon glass layer.

Abstract: A differential receiver has a switching point accurately set according to a reference voltage, which switching point is dynamically modified, that is, dc hysteresis is provided, by a circuit internal to the differential receiver. Positioning of the resultant hysteresis characteristic about the reference signal is adjusted by establishing a backgate voltage differential between an input transistor and a reference transistor of the differential receiver. A switching circuit is also provided for controlling switching of a hysteresis circuit at the reference signal plus or minus a desired offset. The switching circuit is gated by an output signal of the input transistor.

Abstract: The present invention provides an apparatus and methods for holding a first semiconductor device in proper alignment to a second semiconductor device, whose size is different from the first device, while performing a C4 bond between the two devices. The apparatus for holding the two devices in proper alignment consists of a holding fixture, which includes upper and lower pocket receptacles for receiving the semiconductor devices. The semiconductor devices are placed into the respective upper and lower slots aligned to two or more edges of the holding fixture.

Abstract: A method and apparatus for reducing data expansion during data compression are provided that allow the coding scheme used to compress data to be swapped between two or more coding schemes. Specifically, a coding window is provided that holds data to be compressed, and the compression potential of data entering or exiting the coding window is calculated. When a first threshold compression potential sum of data entering the window is reached, the coding scheme used to compress the data within the coding window is swapped from one coding scheme to another. A new compression potential sum is set based upon the compression potential of data exiting the window. The compression potential sum comprises a running total of the compression potential of data entering the coding window; and the coding scheme used to compress data within the coding window is swapped from one coding scheme to another when the compression potential sum reaches a first predetermined value.

Abstract: An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burning to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation.

Abstract: An apparatus and method of conditioning a CMP polishing pad to ensure consistent polishing throughout the polishing process. In particular, the apparatus consists of a translatable wedge-shaped conditioning plate, having a three point adjustable contact to ensure proper alignment with the polishing pad; a high pressure conditioning spray nozzle to clean the polishing pad and conditioning assembly throughout polishing; and a slurry dispensing nozzle to enhance planarization of the wafer. Further, the frequency of oscillation may be varied by the operator to prevent grooves from forming in the polishing pad.

Abstract: A method of reducing data expansion during data compression is provided that allows the coding scheme used to compress data to be swapped between two or more coding schemes. Specifically, a coding window is provided that allows analysis of the compression potential of data within the coding window. The data within the coding window then is analyzed to determine the compression potential of the data. If the compression potential of the data exceeds a first predetermined value, the coding scheme used to compress the data within the coding window is swapped from one coding scheme to another. Preferably the first predetermined value is programmable and is related to the bit cost required to swap back and forth between coding schemes. The two preferred coding schemes are ALDC Lempel-Ziv 1 coding and a pass-through coding scheme wherein raw data is passed unencoded.

Abstract: An electronic semiconductor module, either memory or logic, having a driver circuit which includes a multiplicity of driver transistors, together with circuitry for simultaneously applying a first positive bias to a first select number of driver transistors to activate them to an operational state, a second positive bias to a second select number of driver transistors to place them in readiness for activation, and a negative bias to the remaining driver transistors to place them in a fully inactive state thereby reducing noise in the driver circuit. The first positive bias is greater than the transistor threshold voltage, preferably greater than two volts, the second positive bias is less than the threshold voltage, preferably less than one volt, and the negative bias is in the order of minus 0.3 volt.

Abstract: The distribution of ultraviolet light irradiated from an illumination source to optical elements of a projection exposure device is varied by an illumination aperture. The illumination aperture is formed with a plurality of openings which may be opened or closed independently to the passage of irradiating light. The size and shape of the opening formed by the plurality of openings of the illumination aperture is determined according to the particular image to be projected.

Abstract: Selective electrical connections between an electronic component and a test substrate are made using an electrical conductive material. The conductive material of the present invention is a dissolvable material, allowing for rework and repair of a wafer at the wafer-level, and retesting at the wafer-level. In addition, the conductive material may also be used in a permanent package, since the conductive material of the present invention provides complete electrical conductivity and connection between the electronic component and the substrate.

Abstract: In a sense amplifier for detecting and amplifying a potential difference between a pair of signal lines (BM(BL), /BM(/BL)), a first pull-down circuit (N20, N21), a pull-up circuit (P10, P11), and a second pull-down circuit (N28, N29) are disposed in the recited order between the pair of signal lines. The pull-up circuit (P10, P11) includes a pair of p-type FETs (P10, P11) which configure a flip-flop, and the sources of the pair of p-type FETs are both connected directly to a first constant-voltage source (Vd).

Abstract: A DRAM includes a plurality of DRAM cells; sense amplifiers respectively corresponding to the plural DRAM cells; and means for activating merely a sense amplifier corresponding to a cell to be accessed among the plural DRAM cells, so that merely sense amplifiers in a number corresponding to a burst length can be activated. As a result an access time and restore time can be shortened, and a precharge time can be shortened.