Abstract: In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels for visual inspection. Also, in accordance with the invention, selected aligned fill shapes are interconnected with vias to form conductive stacks for contacting lower wiring level conductive wires from upper wiring levels in order to perform electrical test probing/diagnostics.

Abstract: A defect detecting circuit of the present invention accelerates comparison and judgment by making an address-information renewing and holding circuit 2′ previously hold outputs (program information) of a program-information holding circuit 1′ at the end of the last operation as address information before renewing and holding addresses in the address-information renewing and holding circuit 2′ and thereby simplifying a configuration of a compare and detection Circuit 3′.

Abstract: According to the preferred embodiment, a device and method is provided for reducing power consumption in memory devices. The preferred embodiment reduces power consumption by providing a sense amplifier that reduces power consumption while providing high performance. In the preferred embodiment, the sense amplifier comprises a bi-directional sense amp that is configurable for use on low power static random access memory (SRAM) devices. The bi-directional sense amp allows the same sense amp to be used for both read and write operations on the memory cells. The preferred embodiment sense amp facilitates the use of differential data buses, further reducing power consumption while providing high performance. Thus, the preferred embodiment bi-directional differential sense amp reduces the device size and complexity, reducing power consumption while providing high performance memory access.

Abstract: Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in.

Abstract: A multi-probe ring assembly including integral fine probe tips, conductive lines with terminal connection for testing semiconductor devices and a method of construction of the multi-probe ring assembly is described. The method of construction described utilizes the step of etching pits into silicon wafers to produce molds for forming the probe points. Semiconductor machining processes are used to complete the probe ring assembly.

Abstract: Plasma containment is achieved within a region by a containment plate while gas is allowed to flow through this region by openings in the plate. The openings in the plate are larger in two of the cross-sectional dimensions parallel to the plate surface than the thickness of the dark space or plasma sheath. The openings of the plate are wider nearest the source of the electromagnetic energy in order to attenuate the electromagnetic fields and thereby prevent build up of deposits which would block the flow gas through the plate.

Abstract: A method for sorting integrated circuit chips. At least one physical defect is detected in the semiconductor chips. The semiconductor chips are sorted based upon the physical defect.

Abstract: A SRAM module provides programmability of AC timings such that an end user can adjust or “tweak” the AC timings to maximize system performance. A variable delay circuit is placed in the path between a signal (e.g., data signal or address signal)and the SRAM set-up and hold register which allows the user to shift the setup-and-hold window by selected increments. The delay circuit can either advance or retard the AC timings. A delay program controlling the delay circuit is selected in one of two ways; either by a default AC timing program stored in a ROM device and preset by the manufacturer, or by a private JTAG instruction and AC programming data input by the user through the JTAG state machine provided on the SRAM chip. Once the optimum delay (or advance) is selected to optimize the SRAM to the cache system this user program may be permanently burned into the default ROM such that the optimum timings are used thereafter as the default.

Abstract: The invention relates to a test circuit, and a test method that provides testing for interconnect capability for chips (100, 110). Each of the chips (100, 110) comprises combinational logic (172, 173, 160, 161, 176, 177) as well as a plurality of scan chains (170, 171, 150, 151, 174, 175). Test data is shifted into the scan chains from pattern generators (180, 181) and is then transmitted from a selected sending chip (100) via its transceiver means (130) to the receiving chip (110). The chip (100) is selected by the selector (120) which is located on chip (100). During an interconnect test sequence, different chips in the test system are selected by the selector (120) for testing.

Abstract: The present invention is a method and apparatus for mechanically bonding a polymer to a convex surface of a substrate to provide intimate contact therebetween for improved energy transport between a transducer on one side of the substrate and a chemical bath on the other. The polymer seals the surface of the substrate from the chemical bath and may have a low adhesion to the substrate. A thin film of the polymer is brought under a tensile stress to provide intimate physical contact with most of the area of the convex surface. In one embodiment, the tensile stress is achieved by providing polymer as a liquid on the convex surface and then cooling to take advantage of differential thermal contraction between the polymer and the substrate to achieve the tensile stress in the polymer.

Abstract: An output MUX for a high speed memory is provided with an interlock circuit to insure that only one data bit can be on the output line at a given time. A plurality of data lines are switched, one at a time, onto a single output line by switching transistors in response to one of a plurality of control inputs. A pair of cross-coupled NAND gates are connected to the output line to produce an LOCK signal whenever data is detected on the output line. The LOCK signal is logically NANDed with each of the control inputs prior to reaching the switching transistors. In this manner, the control signals are effectively locked out and not allowed to propagate through to the switching transistors while the output line is already being driven by data. As long as the LOCK signal remains active any of the control inputs may switch without causing any glitches or fails on the output line.

Abstract: An interposer for making a penetrating temporary contact between the contact pads of a chip having bumped or unbumped I/O pads and a test board for the purpose of testing said chip is disclosed. The interposer comprises a silicon substrate having sharp penetrating structures integrally formed at a predetermined depth in the silicon substrate along crystallographic planes. The resultant apparatus has a matching lateral thermal expansion to the chip being tested and provides uniform contact to all chip I/O pads.

Abstract: In a chemical mechanical polishing process for planarization of semiconductor wafers, a pair of opposed grippers are used to move the wafer from one station to another. During this movement, the wafer is rotated and brushes along the periphery are placed in contact with the edge of the wafer to remove foreign material and residue which builds up along the edge of the wafer. Cleaning fluid may be introduced to flush away and/or breakup the residue buildup.

Abstract: A high speed and low power consumption associative memory (CAM) cell and CAM word circuit which provides an associative memory (CAM) word circuit 40. The circuit includes a word match line 20 and a plurality of associative memory (CAM) cells 35 connected in parallel to the word match line. A precharge circuit 21 charges the word match line 20, and a voltage controlling device 41 is located between the precharge circuit and the word match line.

Abstract: A high bandwidth DRAM is provided with two separate bus networks connecting the DRAM to a processor. One bus network is a high speed (e.g., 500 MHZ) 8:1 or 16:1 multiplexed I/O bus and the second is a slower (e.g., 64-bit) bus. The high-speed bus is used for example for graphic intensive applications which require fast access to large numbers of bits in the DRAM memory array. This of course results in higher power requirements. Since, not all applications require such large amounts of data to be transferred between the DRAM and the processor, the slower bus is provided for these less demanding applications such as word processors, spreadsheets, and the like. The slower bus requires less power to operate and therefore results in a power saving mode which, among other things, facilitates longer battery life.

Abstract: An integrated semiconductor module of reduced impedance and method utilizing a given chip architecture of the type having a memory circuit and a plurality of off-chip drivers and their I/O pads, the module being constructed in a configuration for operation of said memory circuit with less than the number of available drivers such that there are a number of excess drivers and output pads not used for driver operations, and one or more of these excess drivers and their pads are connected to the power terminals of the chip to provide one or more power paths through these drivers and their associated pads in parallel with the power paths of the operational drivers, and the method includes connecting the excess drivers and their output pads to the power terminals of the chip during its fabrication in a manner to provide additional power paths.

Abstract: A method and apparatus for selectively causing each bank of a number of banks of DRAMs of a DRAM memory card to enter into the self-refresh mode without affecting the operation of any other bank. In the computer system incorporating the SIMM or DIMM type DRAM cards, each bank of memory on each card has a RAS signal specific to that specific bank. One or more CAS signals are supplied across all of the memory banks, on all cards. Thus, each memory bank is accessed separately for a read/write operation by the RAS becoming active before the CAS becomes active; and refresh takes place by the CAS signal becoming active before the RAS signal becomes active. The number of clock cycles or refresh cycles between active RAS signals to each memory bank are counted.

Abstract: A memory device to perform a plurality of data transfers during a single memory cycle without extending the cycle time for memory access, and to enhance the data transfer rate.A memory array 1 has a plurality of word lines, a plurality of bit lines divided into a predetermined number of groups, and a plurality of memory cells. The bit lines are grouped based on a residue obtained by dividing a column address designating a bit line by the number of groups. The column address decoder 4 generates column addresses of the group number in accordance with the column address signal and an access order signal designating the access order for the groups. When the access order signal designates the ascending order, the bit line selection means 3 generates sequential column addresses, in a number equivalent to the group number and in the ascending order, with the column address signal serving as a reference.

Abstract: An off-chip driver (OCD) circuit including a clamp circuit to limit overdrive is provided. The circuit comprises an input signal which is inverted to provide an output signal. The driver circuit is comprised of a source-follower transistor to pull-down the output signal. The clamp circuit actively feeds back the source-follower potential to slow down the OCD and minimize ground bounce and noise that causes circuits to fail and signal integrity to be corrupted. The simple drive and clamp circuit is comprised of three transistors, one resistor, and one capacitor. The OCD slew rate is controlled by a current source and provides an output that changes between a positive voltage and ground. The circuit limits dv/dt without using a large resistor as a source follower, hence minimizing the adverse effect on performance.

Abstract: A DRAM system is described that can prevent a substantial reduction in bandwidth with respect to a clock pulse frequency even when banks are accessed in no specific order. As a result, provided is a memory system constituted by DRAM whereby a seamless operation is assured not only for reading but also for writing.