Abstract: A caching mechanism for a virtual persistent heap is described. A feature of a virtual persistent heap is the method used to cache portions of the virtual persistent heap into the physical heap. The caching mechanism may be effective with small consumer and appliance devices that typically have a small amount of memory and that may be using flash devices as persistent storage. In the caching mechanism, the virtual persistent heap may be divided into cache lines. A cache line is the smallest amount of virtual persistent heap space that can be loaded or flushed at one time. Caching in and caching out operations are used to load cache lines into the heap or to flush dirty cache lines into the store. Different cache line sizes may be used for different regions of the heap. Translation between a virtual persistent heap address and the heap may be simplified by the caching mechanism. All references may be kept in one address space, the virtual persistent heap address space.

Abstract: A data storage subsystem including a storage disk array employing dynamic data striping. A data storage subsystem includes a plurality of storage devices configured in an array and a storage controller coupled to the storage devices. The storage controller is configured to store a first stripe of data as a plurality of data stripe units across the plurality of storage devices. The plurality of data stripe units includes a plurality of data blocks and a parity block which is calculated for the plurality of data blocks. The storage controller is further configured to store a second stripe of data as a plurality of data stripe units across the storage devices. The second plurality of data stripe units includes another plurality of data blocks, which is different in number than the first plurality of data blocks, and a second parity block calculated for the second plurality of data blocks. Furthermore, the second plurality of data blocks may be a modified subset of the first plurality of data blocks.

Abstract: A storage system may include a plurality of storage devices each having a plurality of addressable locations for storing data. A storage controller may be coupled to the storage devices and configured to store and retrieve data from the storage devices. An indirection map may be stored within the system having a plurality of map entries each configured to map a virtual address to a physical address on the storage devices. Each map entry may also store a checksum for data stored at the physical address indicated by the map entry. The storage controller may receive storage requests specifying a virtual address and may access the indirection map for each storage request to obtain the corresponding physical address and checksum. Dynamic striping may be employed so that new writes form new parity groups. Thus, stripes of various sizes may be supported by the storage system.

Abstract: A routing scheme using intention packets is contemplated. At times, one or more switching devices within a network may become overloaded with traffic or may encounter other adverse transmission conditions. When this occurs, a switching device may drop one or more packets to alleviate some of the congestion or other adverse condition. The switching devices may support a particular amount of resources (e.g. bandwidth, buffers, etc.) in and out of each of their ports. When a packet or a header portion of a packet arrives at a switching device, the switching device may determine what port the packet will need and the amount resources required by the packet on that port. If the required resources available for the packet on the port, then the switching device may route the packet to a next device. If the required resources are not available for the packet on the port, then the switching device may drop at least a portion of the packet. As opposed to or in addition to congestion (e.g.

Abstract: Apparatus, methods, systems and computer program products are disclosed that optimize the application of deferred image operations on a tiled source image. The invention dynamically creates a data structure (such as a directed acyclic graph (DAG)) representing the operations performed on various instances of one or more images to create a final image. The invention analyzes the data structure to determine which source image tiles are needed when the actual image data comprising the final image is required. Each of these tiles are then separately processed by all of the deferred operations to create the final image data. This approach reduces the number of times a tile is read into memory for processing and improves the performance of deferred image operations on a tiled source image.

Abstract: A structure and an improved isolation trench between active regions within the semiconductor substrate involves forming on a silicon substrate and forming a nitride layer on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into a portion of the trench liner to form an oxynitride layer. After formation of the oxynitride layer, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.

Abstract: Several embodiments of a computer system are described which achieve separation of control and data paths during data transfer operations, thus allowing independent scalability of storage system performance factors (e.g., storage system iops and data transfer rate). In one embodiment, the computer system includes a data switch coupled between a host computer and one or more storage devices. A storage controller for managing the storage of data within the one or more storage devices is coupled to the switch. The switch includes a memory for storing data routing information generated by the controller, and uses the data routing information to route data directly between the host computer and the one or more storage devices such that the data does not pass through the storage controller. Within the computer system, information may be conveyed between the host computer, the switch, the one or more storage devices, and the storage controller according to a two party protocol such as the Fibre Channel protocol.

Abstract: A clamping circuit and method for use in a computer system are provided. In the computer system, a voltage regulator supplies a voltage rail to various components in the system. This voltage rail may be susceptible to voltage spikes or other over-voltage conditions, such as when the voltage rail provides the input voltage to a switching regulator. The clamping circuit comprises a detecting stage and a clamping stage. The detecting stage detects when the voltage rail increases beyond a first voltage level. If this increase is detected, the detecting stage activates the clamping stage, which begins reducing the voltage rail. Once the voltage rail decreases beneath the first voltage level, the detecting stage stops activating the clamping stage. In this way, the clamping circuit protects the computer system from voltage spikes on the voltage rail.

Abstract: A system for managing storage accesses for rate guaranteed continuous multimedia data streams and non-rate-guaranteed storage requests may include a plurality of rate guaranteed requestors for multimedia streams and one or more non-rate guaranteed requesters. A disk scheduler may also be included. The disk scheduler may have a guaranteed rate queue for queuing storage requests from the rate guaranteed requestors and a non-rate-guaranteed queue for queuing requests from the non-rate-guaranteed requestors. The disk scheduler may also include a bandwidth allocator coupled to the guaranteed rate queue and the non-rate-guaranteed queue and further coupled to a storage system. The bandwidth allocator may be configured to allocate bandwidth of the storage system between the guaranteed rate queue and the non-rate-guaranteed queue according to a predetermined ratio.

Abstract: A household dishwasher that includes a drain pan designed to relocate leaking fluids to an observable location. The dishwasher is a standard dishwasher with a drain pan for collecting water that unintentionally falls from the interior of the dishwasher. The drain pan is angled for diverting the collected water to a predetermined location exterior to the household dishwasher where an occupant of the household may view the water.

Abstract: A storage array interconnection fabric may be configured using a torus topology. A storage system including a path-redundant torus interconnection fabric is coupled to a plurality of nodes. The torus interconnection fabric may be configured to connect the plurality of nodes in an array including N rows and M columns, where N and M are positive integers. The array may be configured such that a first node in a first row of the N rows is connected to a second node in the first row and a first node in a first column of the M columns is connected to a second node in the first column. Also an ending node in the first row is connected to the first node in the first row and an ending node in the first column is connected to the first node in the first column. In addition, a first portion of the plurality of nodes is configured to communicate with a plurality of storage devices such as disk drives.

Abstract: A mechanism for controlling threads in a Java application while avoiding the unsafe conditions inherent in the use of existing java.lang.Thread methods. In one embodiment, a first class is defined for handling threads in an application. The first class uses a target variable to indicate whether a thread should continue to run, or whether it should be stopped. This first class provides a start( ) method to set up the target variable, a stop( ) method to set the target variable to indicate that the thread should be stopped, and an abstract run( ) method. The functionality of the run( ) method is provided by one or more additional classes which extend the first class. The additional classes override the abstract run( ) method and define the tasks to be performed by threaded objects instantiated from these classes. When a thread needs to be stopped, the corresponding target variable is set to indicate that it should be stopped.

Abstract: The present invention comprises an improved telephone system and method that determine the identity of the callee of an incoming telephone call. A distinctive ring is selected by one or more of the users of the telephone prior to activating the feature or at a later time. Information about the individual distinctive ring signals is stored in memory inside the telephone. When an incoming call is received from an external party, the telephone determines which one of the users is the callee of the telephone call. A distinctive ring signal is then generated corresponding to the identified callee of the incoming telephone call. The distinctive ring signal identifies the callee of the incoming telephone call to the telephone users. In order to identify the callee of the incoming telephone call, the telephone system, after answering the incoming telephone call, inquires the caller for the identity of the callee. In another embodiment, a callee is identified using voice recognition techniques.

Abstract: A computer system includes a real-time interrupt that causes the operating system to determine which isochronous tasks are pending. In one embodiment, applications that include isochronous tasks are certified to be well-behaved and the operating system will only initiate applications that are known to be well-behaved by checking a list of certified applications. The operating system will not initiate an application if insufficient resources are available for executing the tasks of the application. Each application informs the operating system of an execution rate and a maximum duration of its isochronous tasks. Prior to initiating an application, the operating system verifies that resources are available to execute the isochronous tasks of the application. The operating system includes a non-maskable interrupt to terminate isochronous tasks. Termination may be necessary if an isochronous task fails to execute within its specified maximum duration.

Abstract: The present invention comprises an improved telephone system and method that reduce call interruptions to a telephone, i.e., reduce interruptions caused by a caller placing a call to the telephone. If the no-call feature is enabled and a call is received by the telephone, the telephone answers the incoming telephone call in response to receiving the telephone call. The telephone then plays a message to the caller indicating that no calls are being taken. The telephone plays the message after the telephone answers the incoming telephone call. The telephone does not generate an audible ring signal in response to the telephone call received from the caller. The telephone system further comprises an exemption logic unit for allowing calls placed by certain callers to come through even when the no-call feature is enabled. The user indicates the exception parties to the no-call feature prior to receiving a call from an external party or at a later time.

Abstract: Several systems and methods are described for accessing one of multiple groups of peripheral devices. One of the systems includes a host system, multiple peripheral devices, and a host adapter. The peripheral devices are arranged to form multiple groups, each group including at least one peripheral device. The host system is coupled to the peripheral devices via the host adapter, and accesses the peripheral devices via the host adapter. The peripheral devices of each group receive a group access signal for controlling accesses from the host system. The host adapter includes a control register and signal routing logic. The signal routing logic is coupled to the control register and to each of the groups of peripheral devices. The control register stores a value for selecting one of the groups of peripheral devices. The host system may include a central processing unit (CPU) configured to write the value to the control register.

Abstract: Various embodiments of a method and system for sharing a cache such as an on-chip L1 cache are disclosed. In one embodiment, a processing device includes a shared cache and a plurality of processors that are each coupled to the shared cache and each configured to store the result of a data integrity operation in the shared cache. Each of the processors performs the same data integrity operation on the same data to generate its result. Because the results are stored in the shared cache, a first processor may quickly access and operate on the results. In one embodiment, the first processor may perform a comparison operation or voting operation on the results stored in the shared cache.

Abstract: A method implemented in a computer system for storing non-volatile configuration information (NVCI), wherein NVCI is stored in one or more active segments of a segmented flash memory. The NVCI consists of a series of key-value pairs. When the computer system is started, the key-value pairs are read from the active segment, beginning with the least recently stored and ending with the most recently stored. The key-value pairs are inserted into a hash table, with later-read key-value pairs replacing earlier-read key-value pairs of the same key. Write accesses to the NVCI are made to both the hash table and the active segment of flash memory. When an active segment of the flash memory is filled to a threshold capacity, current key-value pairs stored in the hash table are written to a new flash memory segment, which then becomes the active segment.

Abstract: One embodiment of a storage controller is described including a controller memory, one or more central processing units (CPUs), and a host bus adapter all coupled to a controller bus. The one or more CPUs are configured to produce data routing information dependent upon a data transfer command which directs a transfer of data between a host computer and one or more storage devices. The host bus adapter includes a receive unit and a transmit unit adapted for coupling to a transmission medium. The host bus adapter receives the data routing information, and forwards data associated with the data transfer command from the receive unit to the transmit unit dependent upon the data routing information such that the data associated with the data transfer command is not conveyed upon the controller bus and is not stored within the controller memory.

Abstract: A storage system is described including a two dimensional array of disk drives having multiple logical rows of drives and multiple logical columns of drives, and at least one drive array controller configured to store data in stripes (e.g., across the logical rows). A given drive array controller calculates and stores: row error correction data for each stripe of data across each one of the logical rows on one of the drives for each row, and column error correction data for column data grouped (i.e., striped) across each one of the logical columns on one of the drives for each column. The drive array controller may respond to a write transaction involving a particular row data stripe by calculating and storing row error correction data for the row data stripe before completing the write transaction.