Abstract: A semiconductor process for producing two gate oxide thicknesses within an integrated circuit in which a semiconductor substrate having a first region and a second region is provided. The first region and the second region are laterally displaced with respect to one another. A nitrogen species impurity distribution is then introduced into the first region of the semiconductor substrate. Thereafter, a gate dielectric layer is grown on an upper surface of the semiconductor substrate. The gate dielectric has a first thickness over the first region of the semiconductor substrate and a second thickness over the second region of the semiconductor substrate. The first thickness is less than the second thickness. In a CMOS embodiment of the present invention, the first region of the semiconductor substrate comprises p-type silicon while the second substrate region comprises n-type silicon.

Abstract: A system and method for searching for documents within spaces in a distributed computing environment are provided. A client sends a lookup message to a space which stores documents. The lookup message may specify desired characteristics, such as a name or partial XML schema, of the stored documents. The documents may include XML service advertisements and XML device advertisements as well as general-purpose XML documents. A set of zero or more documents which match the lookup message are discovered. In one embodiment, the lookup message may include a desired name. If the lookup message includes both a desired name and a desired schema, the set of discovered documents may include both discovered documents having a name that matches the desired name and discovered documents having a schema that matches the desired schema. If the lookup message includes neither a desired name nor a desired schema, the set of discovered documents may include substantially all the documents stored in the space.

Abstract: A voltage-dependent impedance selector compensates for non-linearities that arise when the operating voltage of an electronic circuit changes. The voltage-dependent impedance selector includes a selection stage that selects a impedance based on the operating voltage of the electronic circuit. The selected impedance is connected to an output stage having a resistive value so that the selected impedance and the output stage form a voltage divider. The voltage-dependent impedance selector may, in some embodiments, be used in reference voltage generation or in impedance matching.

Abstract: A heat sink subassembly may include a retainer comprising several attachment points, a heat sink coupled to the retainer, and a force-generating device. The heat sink includes several fins, one of which is shorter than the other fins. The force-generating device is coupled to at least one of the attachment points and to the first fin. The force-generating device is configured to exert a force that keeps the heat sink securely coupled to the retainer when the force-generating device is coupled to the attachment points.

Abstract: A MOSFET transistor having silicide formed on top of a polysilicon gate conductor, on partially exposed sidewalls of the polysilicon gate conductor, and on junction regions in an underlying semiconductor substrate is provided. Opposed sidewalls of the polysilicon gate conductor are surrounded by dielectric sidewall spacers. An upper surface of the dielectric spacers is lower than an upper surface of the polysilicon gate conductor thereby exposing a portion of the sidewall surfaces of the polysilicon gate conductor. A substantial portion of the polysilicon gate conductor, including the top of the gate and the exposed portion of the sidewall surfaces, may then be subjected to a salicidation process. During this process, salicide structures are also formed on the junctions regions. Therefore, silicide may be simultaneously formed on a substantial portion of the polysilicon gate and on junctions regions providing a gate with lower resistivity without consuming the junction regions during salicidation.

Abstract: A method and apparatus for driving a plurality of addressable elements consist of driving and selectively enabling one or more addressable elements arranged as an M×N array using two drivers. A first and a second driver are used to drive first and second signals at slightly different frequencies on a first and a second display conductor. A plurality of pixels, coupled between the first and second display conductors, is addressed according to a pixel location in which the first signal is approximately in phase with the second signal. The pixel scan rate is proportional to the difference between the first and second signal frequencies. The first and second conductors may contain a plurality of delay elements and tap-off points. Conducting lines may be terminated by their characteristic impedance to prevent any reflection of the traveling signals.

Abstract: Computer processes for carrying out almost any process may be defined as a series of steps using a plurality of standardized user-interface screens. These standardized interface screens may be linked together in predetermined orders to implement on a client computer activities for which the standardized screens are appropriate to accomplish a pre-defined process. Any number of computer processes may be developed and deployed using the standard interfaces. The computer process automatically takes a user from screen to screen, prompting the user to review or provide information or take appropriate action. Processes may be represented using metadata. Metadata may provide data to a screen rendering process running on a user's workstation with details on how to render one of a plurality of standard screens in a manner which is specific to a particular process. Metadata may be provided to define the steps of the process for enabling navigational capabilities.

Abstract: A system and method is disclosed for synchronizing threads of execution within a distributed computing environment. Threads of execution within a computer spawn additional threads of execution on separate computers within the distributed computing environment. Each thread may compete for shared resources within the computing environment, thereby creating a need to avoid deadlocks among the local threads. Whereas locals thread exists within a single computing platform, logical threads are created to relate local threads to each other and thereby span the platforms on which the local threads reside. Distributed monitors are created to control access to shared resources by local threads based on logical thread affiliations. Locks within the distributed monitors are assigned to logical threads instead of local threads. Local threads that are each part of the same logical thread will all have access to the shared resource when the lock is assigned to the logical thread.

Abstract: A system and method are presented for selectively conditioning a surface of a polishing pad of a CMP apparatus in order to achieve a desired surface profile of a semiconductor wafer. The semiconductor wafer may be subjected to a CMP operation using the CMP apparatus following the conditioning. The present CMP apparatus includes a polishing pad having an underside surface mechanically coupled to a substantially planar surface of a platen, an abrasive surface, and a measurement system. The platen and abrasive surface may be rotatable about respective rotational axes. The present conditioning method includes selecting a region of an upper “polishing” surface of the polishing pad (e.g., a CMP region) encircling a rotational axis of the platen and bounded by first and second radial distances from the rotational axis of the platen.

Abstract: One embodiment of a transfer node is described, including a first channel port adapted for coupling to a host computer, a second channel port adapted for coupling to a storage controller and one or more storage devices, a central processing unit (CPU) coupled to the first and second channel ports, and a memory coupled to the CPU. The transfer node receives data routing information associated with a data transfer command from the storage controller via the second channel port, wherein the data transfer command directs a transfer of data between the host computer and the one or more storage devices. The transfer node stores the data routing information within the memory, and routes data associated with the data transfer command between the first and second channel ports using the data routing information stored within the memory.

Abstract: In a method for mounting an integrated circuit onto a substrate in a flip-chip configuration, a circuit alignment feature on the processed surface of the integrated circuit and a substrate alignment feature on the mounting surface of the substrate are used to accurately align a set of bonding pads on the processed surface of the integrated circuit with a corresponding set of contact pads on the mounting surface of the substrate. The positions of the circuit and substrate alignment features are determined, and a separation between these alignment features which will result in accurate alignment of the bonding pads to the corresponding contact pads is calculated. The circuit is moved with respect to the substrate in order to achieve this predetermined separation. The method may be carried out using an apparatus which includes a die placement fixture and a substrate placement fixture.

Abstract: Various methods and systems for cooling high-density arrangements of disk drives are disclosed. A disk drive enclosure includes several stacked layers of disk drives and one or more air movers. Some of the air movers are configured to cool the disk drives by creating an airflow. The disk drives are configured to operate as a network or computer storage system. Instead of being arranged in a traditional, aligned arrangement, the disk drives are arranged in an offset or staggered arrangement so that at least one disk drive in a first layer is offset from an overlapping disk drive in a second layer. The offset is in a direction parallel to the plane that includes the first layer. As a result, at least part of one of the disk drives in the arrangement is exposed to more of the airflow than it would be exposed to in an aligned arrangement.

Abstract: A method and system for improving virtual memory performance, especially in the context of data processing systems utilizing the Accelerated Graphics Port (AGP) interface standard. In the method and system, a request to access a first virtual memory address, correspondent to a first physical memory location resident within a first page of physical memory, is received. In response to the request to access the first virtual memory address, a Graphics Translation Look Aside Buffer entry is created. In response to a request to access a second virtual memory address, correspondent to a second physical memory address resident within a second physical memory area non-overlapping with the first physical memory page, the second physical memory location is accessed via the Graphics Translation Look Aside Buffer entry. The Graphics Translation Look Aside Buffer entry is constructed such that it translates a number of virtual memory addresses corresponding to a number of physical memory addresses.

Abstract: A chemical-mechanical polishing pad conditioning system and method. The system includes a conditioning device that may be used to condition a polishing pad. The system may also include a first conduit for introducing a chemical reagent onto the polishing pad, a second and third conduit for introducing the chemical reagent and a rinsing fluid respectively onto a conditioning surface of the.conditioning device or a storage apparatus of the conditioning device. The method includes introducing the chemical reagent onto the polishing pad during the pad conditioning process. The chemical reagent may further be introduced onto the storage apparatus or be introduced onto the conditioning surface of the conditioning device. The rinsing fluid may be introduced onto the polishing pad, the storage apparatus, or the conditioning surface.

Abstract: A system and method of measuring extinction ratio and deterministic jitter of an optical transceiver. The measurement system includes a computing node and an oscilloscope coupled to the computing node. The oscilloscope is also coupled to the optical transceiver. The oscilloscope is configured to capture a waveform of a predetermined data pattern transmitted by the optical transceiver. The oscilloscope is configured to capture the waveform in a non-persistent mode using waveform averaging. The oscilloscope is also configured to perform measurements on the waveform. The computing node is configured to program the oscilloscope to perform the measurements on the waveform. The computing node is also configured to calculate an extinction ratio and to compare the extinction ratio to an acceptable standard. The computing node is also configured to calculate a deterministic jitter value of the optical transceiver in response to the extinction ratio being within the acceptable standard.

Abstract: Method and system for purging a process line of a process gas used in a semiconductor wafer fabrication process. Inert gas (e.g., nitrogen gas) is repeatedly charged from an inert gas source into the process line and evacuated using a vacuum system. The vacuum system is preferably supplied with inert gas having a pressure in excess of 30 psig from the inert gas source. The inert gas is introduced into the process line from an inert gas conduit at a predetermined pressure to prevent process gas from liquefying in the process line. A set pressure regulator or an absolute pressure regulator may be used to reduce he pressure of the inert gas to below the vapor pressure of the process gas.

Abstract: A cooling device detection circuit and method for detecting a cooling device in a computer system. In one embodiment, a cooling device detection circuit includes a detection stage and a power management stage. The detection stage is configured to sense an indication that the cooling device is functioning and to assert a signal if the cooling device is detected. The power management stage is configured to turn off a component cooled by the cooling device if the cooling device is not detected.

Abstract: A computer system includes a real-time interrupt that causes the operating system to determine which isochronous tasks are pending. In one embodiment, applications that include isochronous tasks are certified to be well-behaved and the operating system will only initiate applications that are known to be well-behaved by checking a list of certified applications. The operating system will not initiate an application if insufficient resources are available for executing the tasks of the application. Each application informs the operating system of an execution rate and a maximum duration of its isochronous tasks. Prior to initiating an application, the operating system verifies that resources are available to execute the isochronous tasks of the application. The operating system includes a non-maskable interrupt to terminate isochronous tasks. Termination may be necessary if an isochronous task fails to execute within its specified maximum duration.

Abstract: An MOS device is provided having a channel-stop implant placed between active regions and beneath field oxides. The channel-stop dopant material is a p-type material of atomic weight greater than boron, and preferably utilizes solely indium ions. The indium ions, once implanted, have a greater tendency to remain in their position than boron ions. Subsequent temperature cycles caused by, for example, field oxide growth do not significantly change the initial implant position. Thus, NMOS devices utilizing indium channel-stop dopant can achieve higher pn junction breakdown voltages and lower parasitic source/drain-to-substrate capacitances. Furthermore, the heavier indium ions can be more accurately placed than lighter boron ions to a region just below the silicon layer which is to be consumed by subsequent field oxide growth. By fixing the peak concentration density of indium at a depth just below the field oxide lower surface, channel-stop implant region is very shallow.