Abstract: A controller for a powered loudspeaker including a bus monitor configured to monitor a bus for activity and a click suppression unit coupled to the bus monitor and configured to control speaker volume by ramping the volume down if an absence of data on the bus is detected, and restoring the volume once bus activity begins again. In this manner, undesired clicks and hisses upon power up and power down are minimized.

Abstract: A method and apparatus for driving a plurality of addressable elements consist of driving and selectively enabling one or more addressable elements arranged as an M×N array using two drivers. The columns may be addressed in parallel. Columns may be coupled to a conductor by a charge transfer/isolation circuit. A voltage waveform or pulse train may be propagated down the display conductor such that a pulse is present on the display conductor for each element of a row of elements to be addressed. When the beginning of the pulse train has propagated to the last column tap-off point so that a different pulse is present at each column tap-off point corresponding to the row of elements to be selected, a corresponding charge is transferred to each column conductor in parallel. Thus, a voltage is supplied to select each element on the selected row as determined by the state of the pulse train at each column tap-off point.

Abstract: In a processor a reorder buffer maintains a load/store (LS) fault address register (LSFAR). When the processor's load/store unit reports most LS exceptions, the reorder buffer redirects the microcode unit of the processor to execute a fault handler indicated by an address stored in the LSFAR. The LSFAR may be mapped into the register space of the processor. It may be written by a microcode routine with the address of a specific fault handler at the beginning of a microcode routine or at any time during a microcode routine. As the reorder buffer retires instructions it checks for writes to the LSFAR. If one exists, the reorder buffer loads the result data of that write into the LSFAR. In a preferred embodiment the reorder buffer retires instructions in program order and the LSFAR is not updated speculatively. Also, in a preferred embodiment, when a microcode routine exits, the LSFAR is automatically returned to a default value which indicates a generic fault handling routine.

Abstract: A system for scheduling storage accesses of multiple continuous media streams may include a plurality of media stream clients. Associated with each media stream client is one of a plurality of media stream managers. Each media stream manager maintains a ring of buffers configured to buffer media stream data between its associated media stream client and one or more storage systems. A different deadline queue may be associated with each one of the storage systems. Each deadline queue may be configured to queue buffer requests from the media stream managers. Each buffer request may include a deadline by which the buffer request must be fulfilled by the corresponding storage system. Each media stream manager may be configured so that once one of its buffers is consumed by the associated media stream client, the media stream manager submits a buffer request and deadline for that buffer to the appropriate deadline queue. Buffer requests may be ordered in each deadline queue from earliest to latest deadline.

Abstract: Random access memory (RAM) may be provided in a processor for implementing microcode patches. The patch RAM may loaded by a microcode routine that is part of the normal microcode contained in a microcode read only memory (ROM) unit of the processor. When the processor powers-up, it uses its internal ROM microcode only if no patches are installed. If patches are installed and a microcode line is accessed for which a patch is enabled, the patch is executed instead of the microcode line. A patch may be enabled by setting a match register with the address of the microcode instruction line in the microcode ROM that is to be patched. Whenever the microcode ROM address matches the contents of a match register, control is transferred to the patch RAM. The patch RAM may have a plurality of fixed entry points each corresponding to a different match register.

Abstract: In an object oriented software environment, a system and method is disclosed that addresses both state recovery and relationship recovery in the event of a system halt. The system is suited to enterprise-class distributed systems with extensive object relationships. Each essential object is saved in persistent storage. Essential values within each object are updated in storage according to a method within each object. After a partial or total halt of the system, the state of the software is reconstructed in a two phase process. In the first phase, the essential objects are restored from persistent storage, along with essential values. In the second phase, a method uniquely implemented by each object will reconstruct non-essential objects and variables. The second phase is ideally tailored to allow the system to be reconstructed even when the underlying hardware or software has been altered.

Abstract: An array of storage devices may be provided in which data is both striped and mirrored across the array. Data may be organized in stripes in which each stripe is divided into a plurality of stripe units. The stripe units may be mapped sequentially to consecutive storage devices in the array for each data stripe. Each data stripe is also mirrored within the array as a mirrored data stripe. Each mirrored data stripe is also divided into a plurality of stripe units. The stripe units of the mirrored stripes are distributed throughout the array according to a mapping that provides for load balancing during a reconstruction operation. According to one embodiment, stripe units for mirrored stripes are distributed according to a rotational group such that each mirrored stripe is rotated on the array by one more position than the previous mirrored stripe and wherein the rotational group is repeated as necessary.

Abstract: A computer system includes a real-time interrupt that causes the operating system to determine which isochronous tasks are pending. In one embodiment, applications that include isochronous tasks are certified to be well-behaved and the operating system will only initiate applications that are known to be well-behaved by checking a list of certified applications. The operating system will not initiate an application if insufficient resources are available for executing the tasks of the application. Each application informs the operating system of an execution rate and a maximum duration of its isochronous tasks. Prior to initiating an application, the operating system verifies that resources are available to execute the isochronous tasks of the application. The operating system includes a non-maskable interrupt to terminate isochronous tasks. Termination may be necessary if an isochronous task fails to execute within its specified maximum duration.

Abstract: A modem configurable to operate in a normal mode to perform data communications on the Public Switched Telephone Network (PSTN) additionally configurable to operate in a duplex speakerphone mode. Preferably, the modem is a Personal Computer Memory Card Industry Association (PCMCIA) card for insertion into a connector in a portable computer. The computer includes a sound system with associated microphone and speaker that is incorporated in or associated with the portable computer as the audio input and output for the speakerphone operation. The modem incorporates an interface which allows digitized audio samples from the coder portion of a voice coder-decoder (CODEC) on the modem to be communicated to the computer and digitized audio samples from the computer's sound system to be communicated to the decoder portion of the modem's CODEC. The interface is configured in a manner which is transparent to the modem's normal data communications functions, i.e.

Abstract: A computer system includes a real-time interrupt that causes the operating system to determine which isochronous tasks are pending. In one embodiment, applications that include isochronous tasks are certified to be well-behaved and the operating system will only initiate applications that are known to be well-behaved by checking a list of certified applications. The operating system will not initiate an application if insufficient resources are available for executing the tasks of the application. Each application informs the operating system of an execution rate and a maximum duration of its isochronous tasks. Prior to initiating an application, the operating system verifies that resources are available to execute the isochronous tasks of the application. The operating system includes a non-maskable interrupt to terminate isochronous tasks. Termination may be necessary if an isochronous task fails to execute within its specified maximum duration.

Abstract: A modular chemical delivery block is presented. In an embodiment, the modular chemical delivery block is a top-accessible modular block. A top-accessible modular block is one that may be coupled to or decoupled from an adjacent modular block using access from directly above the top-accessible modular block. The top-accessible modular chemical delivery block preferably includes an axial connection location configured to allow the modular block to be coupled to a laterally adjacent modular block. The interior surface of the axial connection location is preferably substantially parallel to the exterior surface of the axial connection location and unobstructed by other portions of the modular block from the top surface of the modular block. Another embodiment involves a unified modular block configured to direct multi-directional fluid flow therethrough. The unified modular block preferably includes first and second fluid flow paths having first and second axial bore holes.

Abstract: A transistor and a method for making a transistor are described. A metal layer is formed upon a semiconductor substrate, and a masking layer is formed upon the metal layer. The masking layer is patterned to form an opening therein, and portions of the metal layer not covered by the masking layer are removed. A gate dielectric layer is formed within the opening upon the semiconductor substrate; in an embodiment, spacers are also formed upon opposed sidewall surfaces of the masking layer. A conductive material is then deposited upon the dielectric material to form a gate conductor. The masking material is then removed, source and drain and lightly doped drain impurity areas are formed in the semiconductor substrate, and the metal layer is annealed to form a silicide in close proximity to the channel region. By depositing the metal layer prior to forming the gate conductor, the process described herein allows formation of a metal silicide adjacent or in close proximity to the channel region of the transistor.

Abstract: A system and a method to transfer data between a host computer and a storage device. The storage controller architecture is organized into its functional modules based on whether a module primarily performs a control function or a data transfer function. The data paths that connect various functional units (for example, switching unit, parity logic, memory module, etc.) may then be sized to the required bandwidth. This effectively makes the iops (I/O operations per second) and bandwidth capability of a storage controller scalable independently of each other. A data transfer command from a host computer is decoded and translated into one or more data transfer commands by the control module in the storage controller. The control module then sends a list of translated commands to the host. Parity calculation, caching, one or more RAID levels and other relevant data transfer information may also be included as part of the translated set of commands.

Abstract: Various circuits for shifting the crossing point level of a pair of differential clocks signals are disclosed. In some embodiments, a differential clock driver provides a pair of differential clock signals to a device having a specified valid range for the crossing point of the differential clock signals. A level-shifting device is coupled to one or both of the differential clock signals to shift the crossing point to lie within the valid range. The device may be a memory device in some embodiments, and in certain embodiments the memory device may be DDR SDRAM. A method for configuring a computer system is also disclosed. An actual differential clock crossing point is compared to a specified range for the crossing point. If the actual crossing point is not within the specified range, a level-shifting device is coupled to one or both of the differential clock signals.

Abstract: A detached drain transistor including a semiconductor substrate, a source impurity distribution, a drain impurity distribution, a gate dielectric, and a conductive gate. The source impurity distribution is substantially contained within a source region of the semiconductor substrate. The drain impurity distribution is substantially contained within a detached drain region of the semiconductor substrate. The gate dielectric is formed on an upper surface of the semiconductor substrate. The conductive gate is formed on the gate dielectric and laterally disposed over a channel region of the semiconductor substrate. The channel region extends laterally between the source region of the semiconductor substrate and the detached drain region. The channel boundary of the detached drain region is laterally displaced from a first sidewall of the conductive gate by a detached displacement. Preferably, the gate dielectric is a thermal oxide having a thickness of approximately 20 to 200 angstroms.

Abstract: A system and method for tuning a storage system may include characterizing a maximum sustainable throughput for the storage system. The maximum sustainable throughput may be decreased by a primary derate parameter to obtain a primary throughput. Sizes for buffer units may be determined at different stream rates, where during operation the buffer units buffer a data stream between a stream requester and storage. Buffer unit sizes may be determined by generating stream simulators sufficient to consume the primary throughput and then optimizing the buffer sizes to prevent underruns. This may be repeated at different stream rates to determine a table of buffer sizes. The primary throughput may be decreased by a secondary derate parameter to obtain a maximum system bandwidth which sets an upper limit on admission of streams. When buffer sizes are determined, a prefill margin parameter may be set by which request deadlines must be met.

Abstract: The present invention comprises a telephone system and method that identify and announce the caller and/or the callee of an incoming telephone call. After receiving a telephone call from a caller, the telephone system answers the incoming telephone call. The identity of the caller is then determined. The telephone system prompts the caller to say his/her name. The name is recorded and repeatedly played back through a built-in speaker announcing the name of the caller to the users of the telephone. The telephone system may also ask the caller to say the name of the callee. In that case, the name of the callee is also recorded and repeatedly played back. The name of the caller and the name of the callee are both announced to the users of the telephone.

Abstract: A bracket having two parallel sides and an interconnecting crosspiece is attached to a disk drive or similar peripheral with the sides of the bracket extending longitudinally of the sides of the drive and the crosspiece extending across the front of the drive. A chassis of a computer or the like has internal parallel sides formed with horizontal guides to receive the bracket, a substantially open front face and an internal connector engageable with a mating connector on the rear of the drive when the bracket is fully inserted in the chassis. The sides of the bracket have features to protect the drive from horizontal and vertical vibrations. A handle is pivoted to the crosspiece near one end moveable between at least three positions: a first or latched position parallel to the crosspiece, a second position swinging out at about a 15° angle and a third position at about a 45° angle.

Abstract: An interrupt descriptor cache for a microprocessor is provided which is configured to store interrupt information associated with a plurality of interrupt vectors. Prior to fetching interrupt information from a main memory of a computer system, the microprocessor searches the interrupt descriptor cache. If the interrupt information is stored therein, the address of the interrupt service routine is formed from the stored interrupt information instead of fetching the interrupt information from main memory. The interrupt descriptor cache is additionally configured to monitory memory accesses for updates to the interrupt information stored therein. If a memory location storing interrupt information is updated, then the interrupt descriptor cache invalidates any storage locations which may be storing the information.

Abstract: A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary to produce air gaps during CVD of the dielectric. Air gaps exist between interconnects to reduce the line-to-line capacitance, and thereby reduce the propagation delay associated with closely spaced interconnects.