Patents Represented by Attorney, Agent or Law Firm Robert D. Atkins
  • Patent number: 8093151
    Abstract: A semiconductor wafer has a plurality of semiconductor die. A peripheral region is formed around the die. An insulating material is formed in the peripheral region. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. A conductive layer is formed between the conductive THV and contact pads of the semiconductor die. A noise absorbing material is deposited in the peripheral region between the conductive THV to isolate the semiconductor die from intra-device interference. The noise absorbing material extends through the peripheral region from a first side of the semiconductor die to a second side of the semiconductor die. The noise absorbing material has an angular, semi-circular, or rectangular shape. The noise absorbing material can be dispersed in the peripheral region between the conductive THV.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: January 10, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Shuangwu Huang, Nathapong Suthiwongsunthorn, Dioscoro Merilo
  • Patent number: 8080445
    Abstract: A semiconductor device has a first substrate with a plurality of first conductive vias formed partially through the first substrate. A first semiconductor die is mounted over the first substrate and electrically connected to the first conductive vias. A plurality of bumps is formed over the first substrate. A second substrate has a plurality of second conductive vias formed partially through the second substrate. A penetrable encapsulant is deposited over the second substrate. The second substrate is mounted over the first substrate to embed the first semiconductor die and interconnect structure in the penetrable encapsulant. The encapsulant can be injected between the first and second substrates. A portion of the first substrate is removed to expose the first conductive vias. A portion of the second substrate is removed to expose the second conductive vias. A second semiconductor die is mounted over the second substrate.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: December 20, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Reza A. Pagaila
  • Patent number: 8039303
    Abstract: A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: October 18, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Il Kwon Shim, Seng Guan Chow, Yaojian Lin
  • Patent number: 8039960
    Abstract: An electrical interconnect within a semiconductor device consists of a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, first barrier layer, adhesion layer, and seed layer are formed over the substrate. An inner core pillar including a hollow interior is centered over and formed within a footprint of the contact pad. A second barrier layer and a wetting layer are formed over the single cylindrical inner core pillar and hollow interior. A spherical bump is formed around the second barrier layer, wetting layer, and single cylindrical inner core pillar. A footprint of the spherical bump encompasses the footprint of the contact pad. The spherical bump is electrically connected to the contact pad.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: October 18, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Yaojian Lin
  • Patent number: 8018034
    Abstract: A semiconductor device has a substrate containing a conductive layer. An interconnect structure is formed over the substrate and electrically connected to the conductive layer. A semiconductor component is mounted to the substrate. An encapsulant is deposited over the semiconductor component and interconnect structure. A channel is formed in the encapsulant to expose the interconnect structure. Solder paste is deposited in the channel prior to forming the shielding layer. A shielding layer is formed over the encapsulant and semiconductor component. The shielding layer can be conformally applied over the encapsulant and semiconductor die and into the channel. The shielding layer extends into the channel and electrically connects to the interconnect structure. A docking pin is formed on the shielding layer, which extends into the channel and electrically connects to the interconnect structure. A chamfer area is formed around a perimeter of the shielding layer.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: September 13, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Patent number: 7944302
    Abstract: An apparatus and method for biasing each amplifier of an amplification stage provides that the voltage across each current sensing element of each amplifier of the amplification stage is measured. For each pair of voltage measurements taken, a sum and difference is calculated, where the sum is processed to determine minima peaks and the difference is averaged. A portion of the sum term and the average of the difference term are summed to yield the individual bias current conducted by a first amplifier of the amplification stage. The difference between a portion of the sum term and the average of the difference term is calculated to yield the individual bias current conducted by the second amplifier of the amplification stage. The bias current conducted by the first and second amplifiers may then be individually modified manually, or conversely, may be modified automatically based upon the bias current measurements taken.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: May 17, 2011
    Assignee: Fender Musical Instruments Corporation
    Inventor: Charles C. Adams
  • Patent number: 7897502
    Abstract: A method of making a semiconductor device comprises forming a first conductive layer recessed below a surface of a substrate. The method further comprises forming a second conductive layer raised above the surface of the substrate to create a vertical offset between the first and second conductive layers. The method further comprises forming an interconnect structure on the first and second conductive layers.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: March 1, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: KiYoun Jang, SungSoo Kim, YongHee Kang
  • Patent number: 7880293
    Abstract: A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer exposing the conductive layer, a second via formed in the carrier wafer exposing the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second passivation layers are deposited over the first and second metal layers. The first or second passivation layer has an etched portion to expose a portion of the first metal layer or second metal layer.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: February 1, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Joon Han, Nathapong Suthiwongsunthorn, Pandi Chelvam Marimuthu, Kock Liang Heng
  • Patent number: 7880275
    Abstract: A semiconductor device has a semiconductor die with a peripheral region around the die. A first insulating material is deposited in the peripheral region. A conductive via is formed through the first insulating material. A conductive layer is formed over the semiconductor die. The conductive layer is electrically connected between the conductive via and a contact pad of the semiconductor die. A second insulating layer is deposited over the first insulating layer, conductive layer, and semiconductor die. A profile is formed in the first and second insulating layers in the peripheral region. The profile is tapered, V-shaped, truncated V-shape, flat, or vertical. A shielding layer is formed over the first and second insulating layers to isolate the semiconductor die from inter-device interference. The shielding layer conforms to the profile in the peripheral region and electrically connects the shielding layer to the conductive via.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: February 1, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Rui Huang
  • Patent number: 7875495
    Abstract: A semiconductor device is made by disposing a film layer over a substrate having first conductive layer. An opening is formed in the film layer to expose the first conductive layer. A second conductive layer is formed over the first conductive layer. A first bump is formed over the second conductive layer which promotes reflow of the first bump at a eutectic temperature. A standoff bump is formed on the film layer around a perimeter of the substrate. The film layer prevents reflow of the standoff bump at the eutectic temperature. A second bump is disposed between a semiconductor die and the first bump. The second bump is reflowed to electrically connect the semiconductor die to the first bump. After reflow of the second bump, the standoff bump has a height at least 70% of the second bump prior to reflow to maintain separation between the semiconductor die and substrate.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: January 25, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: TaeWoo Kang, YoRim Lee, TaeKeun Lee
  • Patent number: 7863721
    Abstract: A semiconductor device has first and second wafers having bond pads. The bond pad of the second wafer is connected to the bond pad of the first wafer using a conductive adhesive. A first interconnect structure is formed within the second wafer and includes a first via formed in a back surface of the second wafer to expose the bond pad of the second wafer. A first metal layer is formed conformally over the first via and is in electrical contact with the bond pad of the second wafer. A third wafer is mounted over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first metal layer. A second interconnect structure is formed over a backside of the third wafer opposite the front surface. The second interconnect structure is electrically connected to the first metal layer.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: January 4, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Nathapong Suthiwongsunthorn, Pandi Chelvam Marimuthu
  • Patent number: 7859085
    Abstract: A semiconductor die has a first insulating material disposed around a periphery of the die. A portion of the first insulating material is removed to form a through hole via (THV). Conductive material is deposited in the THV. A second insulating layer is formed over an active surface of the die. A first passive circuit element is formed over the second insulating layer. A first passive via is formed over the THV. The first passive via is electrically connected to the conductive material in the THV. The first passive circuit element is electrically connected to the first passive via. A third insulating layer is formed over the first passive circuit element. A second passive circuit element is formed over the third insulating layer. A fourth insulating layer is formed over the second passive circuit element. A plurality of semiconductor die is stacked and electrically interconnected by the conductive via.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: December 28, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Yaojian Lin
  • Patent number: 7858441
    Abstract: A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) structure is formed over the temporary carrier. The IPD structure includes an inductor, resistor, and capacitor. Conductive posts are mounted to the IPD structure, and first semiconductor die is mounted to the IPD structure. A wafer molding compound is deposited over the conductive posts and the first semiconductor die. A core structure is mounted to the conductive posts over the first semiconductor die. The core structure includes a semiconductor material. Conductive through silicon vias (TSVs) are formed in the core structure. A redistribution layer (RDL) is formed over the core structure. A second semiconductor die is mounted over the semiconductor device. The second semiconductor die is electrically connected to the core structure.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: December 28, 2010
    Assignee: Stats ChipPAC, Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Patent number: 7860910
    Abstract: A floating-point number is encoded into a binary string. A left-to-right comparison of the binary string determines relative magnitude of the floating-point number. If the floating-point number is negative, then take an absolute value of the floating-point number. The resulting binary string conversion is then complemented. If the floating-point number is zero, then a value for the binary string is assigned. The value is a “1” followed by a plurality of “0”s. A portion of each byte of the binary string determines whether another byte follows in the binary string. A value of a bit of each byte of the binary string determines whether another byte follows. In another aspect, the floating-point number encodes to a binary string having a length as a function of the mantissa and exponent of the floating-point number.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: December 28, 2010
    Inventor: Robert S. Howard
  • Patent number: 7858442
    Abstract: A semiconductor package includes a leadframe, an elevated die paddle disposed above the leadframe, a first die attached to a lower surface of the elevated die paddle to support the first die within the semiconductor package, and a second die attached to the first die. A method of manufacturing a semiconductor package includes providing a leadframe having a lower lead and an elevated die paddle structure, attaching a first die to the elevated die paddle structure with a die adhesive (DA) for supporting the first die within the semiconductor package, and wire bonding the first die to the lower lead.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: December 28, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Francis Heap Hoe Kuan, Seng Guan Chow
  • Patent number: 7851345
    Abstract: A semiconductor device has a semiconductor die with a solder bump formed on its surface. A contact pad is formed on a substrate. A signal trace is formed on the substrate. The pitch between the contact pad and signal trace is less than 150 micrometers. An electroless surface treatment is formed over the contact pad. The electroless surface treatment can include tin, ENIG, or OSP. A film layer is formed over the contact pad with an opening over the signal trace. An oxide layer is formed over the signal trace. The film layer and surface treatment prevent formation of the oxide layer over the contact pad. The film layer is removed. The solder bump is reflowed to metallurgically and electrically bond to the contact pad. In the event that the solder bump physically contacts the oxide layer, the oxide layer maintains electrical isolation between the solder bump and signal trace.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: December 14, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: SeongBo Shim, KyungOe Kim, YongHee Kang
  • Patent number: 7851246
    Abstract: A semiconductor package has a semiconductor die with an optically active region which converts light to an electrical signal. An expansion region is formed around the semiconductor die. A through hole via (THV) is formed in the expansion region. Conductive material is deposited in the THV. A passivation layer is formed over the semiconductor die. The passivation layer allows for passage of light to the optically active region of the semiconductor die. A glass layer is applied to the passivation layer. A first RDL is electrically connected between the THV and a contact pad of the semiconductor die. Additional RDLs are formed on a front and back side of the semiconductor die. An under bump metallization (UBM) layer is formed over and electrically connected to the intermediate conduction layer. Solder material is deposited on the UBM and reflowed to form a solder bump.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: December 14, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Lionel Chien Hui Tay, Henry D. Bathan, Arnel Senosa Trasporto
  • Patent number: 7851893
    Abstract: A semiconductor device is made by providing a substrate having an interconnect structure, providing a plurality of semiconductor die each having a through silicon via (TSV), mounting the semiconductor die to the substrate to electrically connect the TSV to the interconnect structure, depositing an encapsulant between the semiconductor die, and forming a shielding layer over the encapsulant and semiconductor die. The shielding layer is electrically connected to the TSV which in turn electrically connects to the interconnect structure to isolate the semiconductor die from interference. The shielding layer is electrically connected to a ground potential through the TSV and interconnect structure. The semiconductor die includes solder bumps which are electrically connected to contact pads on the substrate. The substrate also includes solder bumps electrically connected to a conductive channel in the interconnect structure which is electrically connected to the TSV.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: December 14, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Seung Won Kim, Dae Wook Yang
  • Patent number: 7842542
    Abstract: An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each having a lead frame interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the lead frame interconnect structure and encapsulant. The package interconnect structure and lead frame interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the lead frame interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the lead frame interconnect structure.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: November 30, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Il Kwon Shim, Seng Guan Chow, Heap Hoe Kuan
  • Patent number: RE43075
    Abstract: A headblock and fingerboard support assembly for a stringed instrument includes a fingerboard support assembly for mounting to a neck and fingerboard of the stringed instrument. The fingerboard support assembly further includes a plate having an integrated rail structure. A headblock has an integrated channel for receiving the integrated rail structure. The headblock is adapted to secure to the fingerboard support assembly. A method of assembling a stringed instrument includes mounting a plate structure to a neck and fingerboard of the stringed instrument, where the plate includes an integrated rail, and mounting a headblock to an interior surface of a body of the stringed instrument, where the headblock has an integrated channel structure for receiving the integrated rail of the plate structure.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: January 10, 2012
    Assignee: Fender Musical Instruments Corporation
    Inventors: Kevin M. Kroeger, Meaulnes Laberge, Timothy P. Shaw, Daniel J. Smith, Donald Scott Wade, Jr.