Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.

Abstract: A semiconductor die has a peripheral region around the die. An insulating layer is formed over the semiconductor die. A portion of the insulating layer and peripheral is removed to form a recess around the semiconductor die. A conductive layer is deposited over the insulating layer and recess. The conductive layer is electrically connected to contact pads on the semiconductor die and conforms to a step into the recess. A gap is created through the conductive layer and peripheral region around the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. The conductive THV is recessed with respect to a surface of the semiconductor die. The conductive THV is electrically connected to the conductive layer.

Abstract: A vacuum bonding tool for pick-and-place and bonding semiconductor chips onto a substrate or onto a previously mounted die to form a die stack includes a shank and a suction part. The shank has a vacuum conduit extending from a first end to a second end of the shank. The shank is adapted for cooperative engagement with the suction part at the second end, and the shank has a plate at the second end to support the suction part. The suction part has a surface for contacting a semiconductor chip during pick-and place operation. According to the invention, the suction part is made of an elastically deformable conductive or non-conductive material. In various embodiments, the chip contacting surface of the elastically deformable suction part flat overall, or is concave, of has a flat central region and concave regions.

Abstract: A power MOSFET is provided on a semiconductor die to withstand radiation exposure. The semiconductor die is mounted on a die flag of a leadframe. The MOSFET includes a substrate and epitaxial layer formed over the substrate. A source region is formed in a surface of the semiconductor die. The source region is coupled to the die flag. A contact pad is formed on the source region. A base region is formed in the surface of the semiconductor die adjacent to the source region. The base region is electrically connected to the contact pad. A drain region is formed in the surface of the semiconductor die. The drain region is coupled to a first wire bond pad on the leadframe. A gate structure is formed over a channel between the source region and drain region. The gate structure is coupled to a second wire bond pad on the leadframe.

Abstract: A semiconductor die has a first insulating material disposed around a periphery of the die. A portion of the first insulating material is removed to form a through hole via (THV). Conductive material is deposited in the THV. A second insulating layer is formed over an active surface of the die. A first passive circuit element is formed over the second insulating layer. A first passive via is formed over the THV. The first passive via is electrically connected to the conductive material in the THV. The first passive circuit element is electrically connected to the first passive via. A third insulating layer is formed over the first passive circuit element. A second passive circuit element is formed over the third insulating layer. A fourth insulating layer is formed over the second passive circuit element. A plurality of semiconductor die is stacked and electrically interconnected by the conductive via.

Abstract: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.

Abstract: A wide-band balun device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil and a portion of the second coil oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A first portion of the third coil is oriented interiorly of the second coil. The third coil has a balanced port connected to the third coil between secondhand third portions of the third coil.

Abstract: A semiconductor device has a semiconductor die with a peripheral region around the die. A first insulating material is deposited in the peripheral region. A conductive via is formed through the first insulating material. A conductive layer is formed over the semiconductor die. The conductive layer is electrically connected between the conductive via and a contact pad of the semiconductor die. A second insulating layer is deposited over the first insulating layer, conductive layer, and semiconductor die. A profile is formed in the first and second insulating layers in the peripheral region. The profile is tapered, V-shaped, truncated V-shape, flat, or vertical. A shielding layer is formed over the first and second insulating layers to isolate the semiconductor die from inter-device interference. The shielding layer conforms to the profile in the peripheral region and electrically connects the shielding layer to the conductive via.

Abstract: A system to support a die includes a substrate. A solder resist is disposed over the substrate. A first solder bump is disposed in the solder resist to provide electrical connectivity through the solder resist to the substrate. A second solder bump is formed over the solder resist to correspond with a peripheral edge or a corner of the die. The second solder bump provides standoff height physical support to the die.

Abstract: A bi-directional power switch is formed as a monolithic semiconductor device. The power switch has two MOSFETs formed with separate source contacts to the external package and a common drain. The MOSFETs have first and second channel regions formed over a well region above a substrate. A first source is formed in the first channel. A first metal makes electrical contact to the first source. A first gate region is formed over the first channel. A second source region is formed in the second channel. A second metal makes electrical contact to the second source. A second gate region is formed over the second channel. A common drain region is disposed between the first and second gate regions. A local oxidation on silicon region and field implant are formed over the common drain region. The metal contacts are formed in the same plane as a single metal layer.

Abstract: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.

Abstract: A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer with many die having contact pads disposed on each die. The semiconductor wafer has saw street guides between each die. A trench is formed in the saw streets. The trench extends partially but not completely through the wafer. The uncut portion of the saw street guides below the trench along a backside of the wafer maintains structural support for the semiconductor wafer. The trench is filled with organic material. Via holes are formed in the organic material. Traces are formed between the contact pads and via holes. Conductive material is deposited in the via holes to form metal vias. The uncut portion of the saw streets below the trench along the backside of the semiconductor wafer portion is removed. The semiconductor wafer is singulated along the saw street guides to separate the die.

Abstract: A non-stationary time series model using a likelihood function as a function of input data, base demand parameters, and time dependent parameter. The likelihood function may represent any statistical distribution. The likelihood function uses a prior probability distribution to provide information external to the input data and is used to control the model. In one embodiment the prior is a function of adjacent time periods of the demand profile. The base demand parameters and time dependent parameter are solved using a multi-diagonal band matrix. The solution of base demand parameters and time dependent parameter involves making estimates thereof in an iterative manner until the base demand parameters and time dependent parameter each converge. A non-stationary time series model is provided from an expression using the solution of the base demand parameters and time dependent parameter. The non-stationary time series model provides a demand forecast as a function of time.

Abstract: A semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. A solder bump is formed on the contact pad. An electrostatic discharge (ESD) bump electrode is formed on the contact pad. The ESD bump electrode has a tip. The ESD bump electrode is made with gold. A chip carrier substrate has a contact pad metallurgically connected to the solder bump. The chip carrier substrate also has a ground plate. The ground plate is a low impedance ground point. The tip of the ESD bump electrode is separated from the ground plate by a distance according to ESD sensitivity of the active devices. The distance is determined by a ratio of a discharging threshold voltage for ESD sensitivity of the active device to be protected to an atmosphere discharging voltage.

Abstract: A semiconductor device is manufactured by, first, providing a wafer designated with a saw street guide. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A plurality of via holes is formed in the organic material. Each of the plurality of via holes is patterned to each of a plurality of bond pad locations on the plurality of dies. A conductive material is deposited in each of the plurality of via holes.

Abstract: A semiconductor package is made by providing a wafer having a first electrical contact pad integrated into a top surface of the wafer, forming a through-hole interconnection extending downward from a first surface of the first electrical contact pad, electrically connecting a die to a second surface of the first electrical contact pad, cutting the wafer to form a channel portion and a connecting portion, disposing an encapsulant over the die and the channel portion, backgrinding the wafer to remove the connecting portion and expose a surface of the through-hole interconnection, disposing a second electrical contact pad over the surface of the through-hole interconnection, disposing a dielectric layer along a side surface of the second electrical contact pad, and singulating the wafer into an individual segment containing the die. The dielectric layer is disposed to form a plurality of lands extending across a bottom surface of the semiconductor device.

Abstract: A semiconductor package includes a leadframe. A first lead finger has a lower portion, a connecting portion extending vertically upward from the lower portion, and a substantially flat, top portion. The top portion forms a top terminal lead structure. A second lead finger is electrically connected to the first lead finger. A portion of the second lead finger forms a bottom terminal lead structure. A portion of the second lead finger corresponds to a bottom surface of the semiconductor package. A surface of the substantially flat, top portion corresponds to a top surface of the semiconductor package.

Abstract: A semiconductor package includes a leadframe, an elevated die paddle disposed above the leadframe, a first die attached to a lower surface of the elevated die paddle to support the first die within the semiconductor package, and a second die attached to the first die. A method of manufacturing a semiconductor package includes providing a leadframe having a lower lead and an elevated die paddle structure, attaching a first die to the elevated die paddle structure with a die adhesive (DA) for supporting the first die within the semiconductor package, and wire bonding the first die to the lower lead.

Abstract: An optical sensor package that includes an optical sensor die is mounted by flip chip interconnect onto a lead frame in a “die-down” orientation, that is, with the active side of the optical sensor die facing the lead frame. An opening is provided in the lead frame die paddle (pad), and light passes from outside the package through the opening in the lead frame die pad onto light collection elements on the active side of the chip.