Abstract: A controller that shares an interface with several other controllers connected in a scan topology in a target system may be selected by receiving a selection event and a selection sequence containing selection criteria from a signal line at each of the controllers, wherein the criteria for selection is broadcast to the controllers. A controller is placed online when the received selection criteria matches an activation criteria of the controller.

Abstract: This invention is power supply protection for complex digital circuits employing an external high voltage supply and an internally generated low voltage core logic supply. Precision analog comparators distinguish between short circuit conditions on the internal supply at various ramp down rates including slow brown out decay. Control circuitry protects I/O circuits from exposure to high currents as a result of possible floating gate conditions in the output circuitry.

Abstract: A system comprises a circuit configured to execute instructions and output event data corresponding to the execution of the instructions. The system also comprises a monitoring device coupled to the circuit. The monitoring device receives information about said event data. The event data comprises event data selected from a group consisting of memory events and external events.

Abstract: A method for specifying a signaling protocol to be used by a controller in a group of controllers connected with shared signaling is provided in which the controller is selected based on selection criteria received by the controller and the signaling protocol is specified based on the received selection criteria.

Abstract: Determining operating context of an executed instruction. At least some of the illustrative embodiments are a computer-readable medium storing a debug-trace program that, when executed by a processor, causes the processor to display trace data on a display device (the trace data comprising a plurality of addresses of instructions executed by a target processor), enable a user of the debug-trace program to select an address of the plurality of addresses to create a selected address, and display data based on an operating context proximate in time to when the instruction of the selected address was executed on the target processor.

Abstract: A method, system, and apparatus for debugging throughput deficiency in an architecture using on-chip throughput computations are disclosed. In one embodiment, a system includes a subsystem module of the integrated circuit (e.g., may be a field-programmable gate array), a other subsystem module associated with the subsystem module to execute a specified function of the integrated circuit, an interconnect module comprising a transmission line to associate the subsystem module to the other subsystem module, and a throughput monitor circuit (e.g., may continuously determine the throughput value) located in the integrated circuit and coupled with the interconnect module to measure a throughput value as a specified number of data bits per a specified period of time. The system may include, an interrupt generation circuit located in the integrated circuit and coupled with the throughput monitor circuit to determine whether the throughput value is less than a specified throughput value.

Abstract: The present invention relates to controlling the refresh rate of the reference voltage on a sampling capacitor (Csamp). A comparator (COMP) compares the voltage on a first capacitor (C1) with the voltage on a second capacitor (C2). These capacitors have the capacitance of the sampling capacitor (Csamp). Upon each refresh the first capacitor (C1) samples a first voltage (Va) and the second capacitor samples a lower second voltage (Vb). The first capacitor (C1) is discharged at a first current Ia via a first leakage current source (D1). The second capacitor (C2) is discharged at a second current Ib via a second leakage current source (D2). The comparator (COMP) triggers a refresh when the voltages equal. The first current Ia is preferably an integer N times the second current Ib.

Abstract: Performing series equivalent scans spanning a plurality of scan technologies in a complex scan topology may be performed by performing shift operations in the complex scan topology while only one branch of the complex scan topology connectivity is enabled, and performing capture and update operations in parallel while scan topology connectivity of two or more of the plurality of scan technologies is enabled.

Abstract: A method of wireless communication including a plurality of fixed basestations and a plurality of mobile user equipment with each basestation transmitting to any user equipment within a corresponding cell a sounding reference signal sub-frame configuration indicating sub-frames when sounding is permitted. Each user equipment recognizes the sounding reference signal sub-frame configuration and sounds only at permitted sub-frames. Differing cells may have differing sounding reference signal sub-frame configurations. There are numerous manners to encode the transmitted information.

Abstract: A method of detection is described to be used in file system-based player devices to determine the type of compact disk that has been inserted into a player. The method automatically distinguishes between the DTS-CD format and standard audio CDs. The method allows the operating system or CPU software to take appropriate action to decode and playback the audio stream once the a decision between standard audio CD or DTS-CD is made.

Abstract: An apparatus for monitoring speaker cone displacement in an audio speaker includes: (a) an electromagnetic coil structure; (b) a ferrous core structure; the ferrous core structure and the electromagnetic coil structure being mounted with the speaker to effect variable electromagnetic coupling between the ferrous core structure and the electromagnetic coil structure as the speaker cone moves; (c) a signal injecting circuit coupled with the electromagnetic coil structure for injecting a predetermined input signal into the electromagnetic coil structure; and (d) a signal monitoring circuit coupled with the electromagnetic coil structure; the signal monitoring circuit receiving an output signal from the electromagnetic coil structure and generating an indicating signal based upon the output signal; at least one signal characteristic of the indicating signal being related with the cone displacement.

Abstract: This invention transforms a circuit design at an asynchronous clock boundary using a flow involving register grouping, logic modification and level shifter and isolation cell insertion. The level shifter and isolation cell inserted are tested for proper location. The transformed circuit design is suitable for power consumption control by independent control of separate voltage domains.

Abstract: Clock spreading systems and methods are disclosed. In one embodiment of the invention, a clock spreading system is provided in an integrated transceiver system that comprises a base band control system and a transceiver coupled to the base band control system. The clock spreading system provides a spread clock output signal derived from a clock reference signal for clocking one of the base band control system and the transceiver. The clock spreading system is configured to provide a periodic phase modulated spread clock output signal during receiving of data in a receive mode and a pseudo-random phase modulated spread clock output signal during transmitting of data in a transmit mode.

Abstract: A method of switching a low dropout regulator includes determining an actual active time of a power request from an electronic device; enabling the low dropout regulator in response to said power request at a time corresponding to a start of the actual active time of the power request for an active enabled time having a duration at least the same as the actual active time and long enough to sufficiently settle the output voltage of the low dropout regulator; and disabling the low dropout regulator. In embodiments, the active enabled time is prolonged beyond the actual active time of the power request for all or at least some power requests. An electronic device includes circuits for controlling the switching of a low dropout in the described manner.

Abstract: A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is non-zero and saturates and stops counting at a maximum count when the overflow count reaches the second predetermined number. The counter can be read via a register read operation. The sum of the sum of the first predetermined number of bits and the second predetermined number of bits being an integral multiple of 8 bits.

Abstract: This invention is an integrated circuit having at least one data pin connecting to external circuits. The invention plural operational units each having a normal mode and a stall mode controlled by an enable input. Selection logic selectively enables an operation unit and connects the data input/output of the enabled operation unit to the data pin. The operational units are responsive to a preceding or following key to enter the normal mode. Each operational unit switches between stall mode and the normal mode upon receiving a corresponding predetermined selection number of pulses at while the clock input receives a non-cycling signal. Greater number of pulses deselect all operational units, switch operational units to the normal mode if the correct key is received and switch all operational units to the stall mode.

Abstract: This invention is an input bias control for a module input. A clock detect circuit generates a signal indicating whether an external clock signal is detected. An operational state detect circuit receives this signal and is responsive to an operational state of the module. The operational state detect circuit enables one of a pull-up and pull-down transistor corresponding said operational state of the module. The operational state detect circuit may the input buffer a predetermined time following external clock signal detection, which might be a following transition in the external clock signal. The operational state detect circuit enables the pull-up or pull-down transistor a predetermined time following enabling said input buffer.

Abstract: A method of converting single channel audio (mono) signals to two channel audio (stereo) signals using simple filters and an Intra-aural Time Difference (ITD) is presented. This method does not distort the spectral content of the original signal very much, and has low computation requirements. A variation is proposed which also uses Intra-aural Intensity Difference (IID).

Abstract: Systems and methods for transferring control between programs of different security levels are described herein. Some embodiments include a processor capable of operating at one or more security levels including a first and a second security level, a memory system coupled to the processor (the memory system stores a first program that executes on the processor at the first security level, and a second program that executes on the processor at the second security level), and a register configured to store an entry point address to the first program (wherein an instruction that executes on the processor at the second security level is blocked from writing values to the register). A transfer of control from the second program to the first program is executed if the register provides the entry point address. The transfer of control is blocked if the entry point address is not provided by the register.

Abstract: The present invention is applicable to an electronic device including a master, a slave, a bus coupling the master and the slave and a clock generator for providing a system clock to the master and slave. The clock generator determines whether the received data is correct on a cycle-by-cycle basis. The clock generator suppresses an edge of a next clock cycle of the system clock signal if the data is not to be correct. The clock generator allows the edge of a next clock cycle of the system clock signal if the data is correct.