Abstract: In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate.

Abstract: In one embodiment, a power supply controller forms a compensation current modulates a value of the feedback signal responsively to a value of a timing control signal used to form a clock signal.

Abstract: In one embodiment, an ESD device is configured to include a zener diode and a P-N diode and to have a conductor that provides a current path between the zener diode and the P-N diode.

Abstract: In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening.

Abstract: In one embodiment, a method of forming an MOS transistor includes forming the MOS transistor to have an active region and a termination region. Within the termination region the method includes forming a plurality of trenches having a conductor within the plurality of trenches. The method also includes forming another conductor to make electrical contact to one of the conductors within the plurality of trenches.

Abstract: In one embodiment, a circuit is configured to operate with a communication protocol that has at least three different signal levels wherein different sequences of the three levels identify different elements of the communication protocol. In another embodiment, a modular control block may be used to select the communication protocol and the operation of the circuit.

Abstract: A lighting system comprising a first plurality of fluorescent lamps (17) constituted by a first and a second lamp (20, 21) having a first common terminal (18) which is connected via a first capacitor (22) to a first terminal (12) of a voltage source (11). The system further comprises a second plurality of fluorescent lamps (29) constituted by a third and a fourth lamp (32, 33) having a first common terminal (30) which is connected via a second capacitor (34) to the first terminal (12) of a voltage source (11). The second terminals of the first lamp (20) and third lamp (32) are connected to a first terminal (24) of a third capacitor (25), said third capacitor (25) being connected with its second terminal to the second terminal (13) of the voltage source (11). The second terminals of the second lamp (21) and fourth lamp (33) are connected to a first terminal (36) of a fourth capacitor (37), the fourth capacitor (37) being connected with its second terminal to the second terminal (13) of the voltage source (11).

Abstract: In one embodiment, a flash controller for a camera is configured with a plurality of flash control channels that each control a value of a current through a light source. The value and timing of the current is controlled responsively to control words received by the plurality of flash control channels.

Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.

Abstract: In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.

Abstract: In one embodiment, a PWM controller is configured to inhibit a drive signal responsively to a bulk input voltage remaining at a low value for a time interval.

Abstract: In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.

Abstract: In one embodiment, a plurality of ESD devices are used to form an integrated semiconductor filter circuit. Additional diodes are formed in parallel with the ESD structures in order to increase the input capacitance.

Abstract: In one embodiment, a power supply controller is configured to turn off a first output transistor but inhibit turning off a second output transistor.

Abstract: In one embodiment, a circuit is formed to couple a battery to a charging voltage at least a portion of a time when the charging voltage is greater than zero volts and is less than a first voltage value. The circuit is also formed to decouple the battery from the charging voltage approximately when the charging voltage is greater than the first voltage and also approximately when the charging voltage is no greater than zero volts.

Abstract: In one embodiment, a closed loop control system is caused to operate in an open loop configuration. At some time while operating in the open loop configuration the system detected the presence or absence of a.c. signals in an output signal of the system in order to detect the presence or absence of a failure of a control loop element, such as an output capacitor.

Abstract: In one embodiment, a switching controller uses an auxiliary winding voltage of a transformer to form a signal representative of current flow through a secondary winding of the transformer. The controller is configured to limit a current through a secondary winding to a maximum value.

Abstract: In one embodiment, a Schottky diode is formed on a semiconductor substrate with other semiconductor devices and is also formed with a high breakdown voltage and a low forward resistance.

Abstract: In one embodiment, high doped semiconductor channels are formed in a semiconductor region of an opposite conductivity type to increase the capacitance of the device.

Abstract: In one embodiment, a bi-directional diode structure is formed to have a substantially symmetrical current-voltage characteristic.