Abstract: A method for measuring the thickness of very thin oxide layers on a silicon substrate. A corona discharge source repetitively deposits a calibrated fixed charge density on the surface of the oxide. The resultant change in oxide surface potential for each charge deposition is measured. By choosing a starting value for an assumed oxide thickness, the approximate change in silicon bandbending per corona discharge step is determined. The cumulative changes in bandbending versus oxide surface potential yields an experimental bandbending versus bias characteristic. A theoretical bandbending versus bias characteristic is established. The experimental and theoretical characteristics are matched at predetermined points thereof and then the assumed oxide thickness is iterated until both characteristics superimpose in the silicon accumulation region. The iterated oxide thickness that allows both characteristics to superimpose is the oxide thickness value being sought.

Abstract: A dielectrically isolated semiconductor device which is substantially planar can be manufactured. The structure is useable for integrated circuits wherein a significant savings in surface area can be obtained over prior techniques. The structure is particularly useful for bipolar integrated circuits wherein a semiconductor substrate with an epitaxial layer thereon contains a buried region partially in the substrate and in the epitaxial layer. The emitter and base regions are located in the epitaxial layer above the buried region. The dielectrically isolating region surrounds the emitter and base region at the surface and extends to a depth wherein it intersects with the buried region to fully isolate the device. The buried region is connected as the collector element of the transistor.

Abstract: Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time.Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material.

Abstract: A tester of circuit devices is disclosed which uses commercially available component parts but is capable of high performance testing of hierarchical memory cards requiring data pulses of variable pulse widths at high repetition rates. The tester includes two memories connected to respective shift registers which in turn, feed a multiplexer. The memories handle test timing patterns for respective halves of the basic clock test cycle and are interleaved in operation along with the shift registers. Two opposite-phased outputs of the multiplexer are applied through respective programmable delay networks and pulse generators to the set and reset inputs of a trigger circuit. The trigger circuit provides test data to a dedicated input pin of the device under test.

Abstract: A simultaneous bi-directional transceiver is described. The transceiver comprises two circuits which are disposed at opposite ends of an interchip cable. In response to the application of digital data signals to these circuits, they generate a trilevel voltage at the ends of the interchip cable. Then, in each circuit, a first input to a differential amplifier is generated from the trilevel voltage by a level shifter comprising a first diode and a first constant current sink and a second input to the differential amplifier is derived from the digital data input signal applied to that circuit by a level shifter comprising a second diode and a second constant current source. Finally, the transceiver outputs are generated from the differential amplifier outputs.

Abstract: A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.

Abstract: A multilayered interposer powering board is disclosed for the distribution of required voltage levels to integrated circuit chip modules under conditions of high current demand and heat induced expansions. The interposer board is introduced between the module and its module mounting board. Flexible connector fingers are intermetallically or ohmically connected between a given level of the interposer board and a given power level of the module.

Abstract: A chemical-mechanical (chem-mech) method for removing SiO.sub.2 protuberances at the surface of a silicon chip, such protuberances including "bird's heads". A thin etch stop layer of Si.sub.3 N.sub.4 is deposited onto the wafer surface, which is then chem-mech polished with a SiO.sub.2 water based slurry. The Si.sub.3 N.sub.4 acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si.sub.3 N.sub.4 layer located on the top and at the sidewalls of the "bird's heads" and the underlying SiO.sub.2 protuberances are removed to provide a substantially planar integrated structure.

Abstract: A method is disclosed for making submicron openings in a substrate. A mesa is formed on the substrate by reactive ion etching techniques. A film is deposited over the entire structure and the mesa is selectively etched away to yield a submicron-sized opening in the film. Using the film as a mask, the substrate exposed thereby is reactively ion etched. An example is given for producing an emitter mask for a polycrystalline silicon base bipolar transistor.

Abstract: A semiconductor memory produced in a unipolar technology includes a cell which has a diffusion storage capacitor with one overlying terminal being merged with a bit/sense line, the other capacitor terminal is a diffused region and is coupled through a word transfer device to a word line injector charge source held at a fixed voltage. To provide an organized array of these cells, each bit line cell includes a shared word line charge source held at a fixed voltage and formed at the surface of a semiconductor substrate. A diffusion storage capacitor also is formed at the surface of the semiconductor and spaced apart from the shared charge source. Information is written into each bit line capacitor by applying a voltage of either of two different magnitudes, representing 1 and 0 bits of information, to the respective bit line while a word selection pulse produces an inversion layer at the surface of the substrate between each bit line capacitor and its shared word line fixed voltage charge source.

Abstract: A bipolar logic circuit with superior speed/power characteristics is described. Circuit operation is based on a unique dynamic minority carrier charge exchange mechanism between the input diodes performing the logic and the oppositely poled level shift diode(s) at the input of the transistor output stage. To accomplish this, the input or logic diodes as well as the level shift diode(s) are laid out as large .tau..sub.s diodes with .tau..sub.s being the minority carrier charge storage time constant. Thus, despite very small dc currents during static operation (resulting in an extremely small dc power dissipation) high dynamic switching currents for turning-off as well as for turning-on the output transistors are achieved.

Abstract: A system for automatically testing a plurality of memory arrays on selected memory array testers includes an interactive data entry device for entering array test specifications including characterizing information, DC testing parameters, AC testing parameters and AC test pattern choices for the array. The test specifications are entered in a format which is independent of a particular tester's characteristics. A universal language generator generates a tester independent universal language instruction sequence for carrying out the prescribed tests based upon the entered test specifications. Associated with each tester is a universal language translator which translates the tester independent universal language instruction sequence into an instruction sequence which is particular to the associated tester. The tester dependent instruction sequence may be loaded into the associated tester to produce the test signals for testing the memory array.

Abstract: Miscorrection of triple errors is avoided in a memory system equipped with a single bit error detection and correction/double bit error detection code by providing a double bit error logging technique. The address of each fetched word is logged in which a double bit error is detected. The address of each fetched word in which a single bit error is detected is compared with all logged addresses. If a coincidence is found between the compared addresses, a triple bit error alerting signal is generated and error recovery procedures are initiated.

Abstract: A composite insulator structure separating adjacent layers of patterned metal on an LSI chip is disclosed. The bottom layer of sputtered oxide is thicker than the top layer and is preferably planarized. The top layer is conformal plasma nitride so as to uncover unwanted projections on the underlying metal and prevent interlevel shorting between the patterned layers.

Abstract: A method for fabricating metallurgical contacts is disclosed for making thermocompression bonds to a metallized ceramic substrate on which semiconductor chips are to be mounted and electrically contacted. The method comprises placing a nickel layer on the metallized portion of the substrate and then covering the nickel with an immersion layer of gold. The gold immersion layer is selectively removed from locations where thermocompression-bonded contacts are desired. Removal is accomplished by applying a chemical stripper. Heavy gold is electroplated on said locations and the assemblage is heat treated prior to placement of the thermocompression-bonded contacts.

Abstract: A composite insulator structure separating adjacent layers of patterned metal on an LSI chip is disclosed. The composite insulator consists of a relatively thick layer of sputtered oxide and a thin layer of plasma nitride. The relatively thin layer can be underneath, inside or on top of the thick layer. The relatively thin layer is conformal and able to cover projections on the underlying metal and prevent interlevel shorting between the patterned layers.

Abstract: Disclosed is the use of metal silicide (e.g. Pt-Si) contacts in boron lightly doped P.sup.- type silicon between two contiguous but not adjacent N.sup.+ type regions instead of employing the usual P.sup.+ implanted or diffused channel stoppers. The invention finds a particularly interesting application in polyimide filled deep trench isolated integrated circuits.The trench sidewalls are coated with an insulating material which is removed from the trench bottom at the all contact etch step. The Pt-Si is formed at the bottom of the trenches at the same time that the device contacts are made.

Abstract: An emitter contact structure is disclosed for alleviating forward bias beta degradation in a bipolar transistor. The structure comprises emitter contact metallurgy which travels over a dielectric insulating layer having an area of increased thickness adjacent to the area of contact between the metallurgy and the emitter.

Abstract: An edge triggered polarity hold, clocked latch circuit is disclosed which requires the use of only a single clock line for operation. The latch circuit comprises three set-reset type latches. Each of two latches receives one set and one reset signal. The third latch receives two reset signals and one set signal. A single clock signal is applied jointly to a reset terminal of the third latch and of one of the first two latches. A data signal is applied to the set terminal of the third latch. The other of the first two latches constitutes the output latch and is connected to receive the outputs of the remaining latches. The output latch produces an output equal to an input data signal upon each occurrence of the leading edge of an input clock signal. The output is held (latched) until the occurrence of the next clock signal when the output becomes equal to the then existing input data signal.

Abstract: Disclosed is an integrated circuit electrode memory array having a plurality of FET memory cells arranged in rows and columns and formed on the same integrated circuit chip with associated support circuits. Each memory cell of the array has a capacitive storage region, an adjacent channel region, and a gate region for controlling the transfer of binary information through the channel region in and out of the capacitive storage region. Each memory cell also has a bit line contact region which is shared with an adjacent memory cell. The word lines are arranged in rows in a substantially equidistant parallel relationship, each word line passing, in succession, over the storage region of a first one of the memory cells and electrically integral with the gate region of a second one of the memory cells.